NOVEMBER 2009
AS7C164A
8K X 8 BIT HIGH SPEED CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER
VCC for Data Retention
Data Retention Current
Chip Disable to Data
Retention Time
Recovery Time
tRC* = Read Cycle Time
SYMBOL
TEST CONDITION
VDR
CE# ≧ VCC - 0.2V
or CE2 ≦ 0.2V
VCC = 2.0V
IDR CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V
Others at 0.2V or VCC-0.2V
tCDR
See Data Retention
Waveforms (below)
tR
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE# controlled)
MIN.
2.0
-
0
tRC*
TYP. MAX. UNIT
-
5.5
V
0.6
3
mA
-
-
ns
-
-
ns
Vcc
CE#
Vcc(min.)
tCDR
VIH
VDR ≧ 2.0V
CE# ≧ Vcc-0.2V
Vcc(min.)
tR
VIH
Low Vcc Data Retention Waveform (2) (CE2 controlled)
Vcc
CE2
Vcc(min.)
tCDR
VIL
VDR ≧ 2.0V
CE2 ≦ 0.2V
Vcc(min.)
tR
VIL
NOVEMBER/2009 V1.2
Alliance Memory Inc
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