SC1480A Просмотр технического описания (PDF) - Semtech Corporation

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SC1480A

DDR and DDR Memory VTT power Supply Controller

Semtech Corporation 

SC1480A

POWER MANAGEMENT

Applications Information

+5V Bias Supplies

The SC1480A requires an external +5V bias supply in

addition to the battery. If stand-alone capability is

required, the +5V supply can be generated with an

external linear regulator such as the Semtech LP2951.

.or optimal operation, the controller has its own ground

reference, VSSA, which should be tied by a single trace

to PGND at the negative terminal of the output

capacitor (see Layout Guidelines). All external components

referenced to VSSA in the Typical Applications Circuit on

Page 1 should be connected to VSSA. The supply

decoupling capacitor should be tied directly between the

VCCA and VSSA pins. A 10Ω resistor should be used to

decouple VCCA from the main 5V supply, which may or

may not be the same 5V supply that powers VDDP. PGND

can then be a separate plane which is not used for

routing traces. All PGND connections are connected

directly to the ground plane with special

attention given to avoiding indirect connections which

may create ground loops. As mentioned above, VSSA

must be connected to the PGND plane at the negative

terminal of the output capacitor(s) only. The VDDP input

provides power to the upper and lower gate drivers. A

decoupling capacitor is required. No series resistor

between VDDP and 5V is required. See layout guidelines

for more details.

an internal on-time capacitor. The on-time is the time

required for the voltage on this capacitor to charge from

zero volts to VOUT, thereby making the on-time of the

high-side switch directly proportional to output voltage

and inversely proportional to input voltage. This

implementation results in a nearly constant switching

frequency without the need for a clock generator.

.or VOUT < 3.3V:

t ON

=

3.3x10−12

• (RTON

+

37x103 ) •



VOUT

VBAT



+

50ns

RTON is a resistor connected from the input supply (VBAT)

to the TON pin. Due to the high impedance of this

resistor, the TON pin should always be bypassed to VSSA

using a 1n. ceramic capacitor.

Enabling

RE.IN enables the RE.OUT buffered reference

(assuming VCCA is present) and VDDP enables the VTT

output (assuming VCCA and RE.IN are present). It is usual

to use a resistor divider from VDDQ to generate RE.IN,

so if VDDQ is not present, neither RE.OUT nor VTT will be

present. .or S3 mode, VDDP may be removed, disabling

VTT but leaving RE.OUT present.

Current Limit Circuit

Pseudo-fixed .requency Constant On-Time PWM

Controller

The PWM control architecture consists of a constant on-

time, pseudo fixed frequency PWM controller (see .igure

1, SC1480A Block Diagram). The output ripple voltage

developed across the output filter capacitor’s ESR

provides the PWM ramp signal eliminating the need for a

current sense resistor. The high-side switch on-time is

determined by a one-shot whose period is directly

proportional to output voltage and inversely proportional

to input voltage. A second one-shot sets the minimum

off-time which is typically 400ns.

On-Time One-Shot (tON)

The on-time one-shot comparator has two inputs. One

input looks at the output voltage, while the other input

samples the input voltage and converts it to a current.

This input voltage-proportional current is used to charge

Current limiting of the SC1480A can be accomplished in

two ways. The on-state resistance of the low-side

MOS.ETs can be used as the current sensing element

or sense resistors in series with the low-side sources

can be used if greater accuracy is desired. RDS(ON)

sensing is more efficient and less expensive. In both

cases, the RILIM resistors between the ILIM pin and LX pin

set the over current threshold. This resistor RILIM is

connected to a 10µA current source within the SC1480A

which is turned on when the low side MOS.ET turns on.

When the voltage drop across the sense resistor or low

side MOS.ET equals the voltage across the RILIM resisor,

positive current limit will activate. The high side MOS.ET

will not be turned on until the voltage drop across the

sense element (resistor or MOS.ET) falls below the

voltage across the RILIM resistor. In an extreme over-

current situation, the top MOS.ET will never turn back

on and eventually the part will latch off due to output

undervoltage (see Output Undervoltage Protection).

 2003 Semtech Corp.

7

www.semtech.com

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