FLASH
AS29F040
FIGURE 7: TEST CONDITIONS,
Test Setup
TABLE 6: TEST CONDITIONS,
Test Specifications
CONDITIONS
Output Load
Output Load Capacitance, CL
(including jig capacitance)
Input Rise and Fall Times
Input Pulse Levels
Input timing measurement
reference levels
Output timing measurement
reference levels
-55 ALL OTHERS UNIT
1 TTL Gate
30
100
pF
5
20
ns
0.0 - 3.0 0.45 - 2.4
V
1.5
0.8, 2.0
V
1.5
0.8, 2.0
V
AC CHARACTERISTICS: Read-Only Operations
PARAMETER
Read Cycle Time3
Address to Output Delay
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High Z2, 3
Output Enable to Output High Z2, 3
Output Enable Hold Time3
Output Hold Time From Addresses
CE\ or OE\, Whichever Occurs First
SYMBOL
JEDEC Std
tAVAV tRC
TEST SETUP
MIN
SPEED OPTIONS1
-55 -70 90 -120 -150 UNITS
55 70 90 120 150 ns
tAVQV tACC
CE\ = VIL
OE\ = VIL
MAX 55
70
90 120 150
ns
tELQV tCE OE\ = VIL MAX 55 70 90 120 150 ns
tGLQV tOE
MAX 30 30 35 50 55 ns
tEHQZ tDF
MAX 18 20 20 30 35 ns
tGHQZ tDF
18 20 20 30 35 ns
Read
MIN 0
0
0
0
0
ns
tOEH Toggle and
Data Polling
MIN
10
10
10
10
10
ns
tAXQX tOH
MIN 0
0
0
0
0
ns
NOTES:
1. See Figure 7 and Table 6 for test specifications.
2. Output driver disable time.
3. Not 100% tested.
AS29F040
Rev. 2.3 01/10
15
Micross Components reserves the right to change products or specifications without notice.