ILX531A
Pin Description
Pin No. Symbol
Description
1 φCLP-ODD Clock pulse input (odd pixel)
2 φRS-ODD Clock pulse input (odd pixel)
3 φLH-ODD Clock pulse input (odd pixel)
4 GND
GND
5 VOUT-ODD Signal out (odd pixel)
6
VGG
Output circuit gate bias
Pin No. Symbol
12 VDD
13 φ1-EVEN
14 GND
15 φ2-EVEN
16 NC
17 VDD
Description
12V power supply
Clock pulse input (even pixel)
GND
Clock pulse input (even pixel)
NC
12V power supply
7 GND
GND
18 VOUT-EVEN Signal out (even pixel)
8 φ2-ODD Clock pulse input (odd pixel)
19 VDD
12V power supply
9 φ1-ODD Clock pulse input (odd pixel)
20 φLH-EVEN Clock pulse input (even pixel)
10 VDD
12V power supply
21 φRS-EVEN Clock pulse input (even pixel)
11 φROG Readout gate clock pulse input 22 φCLP-EVEN Clock pulse input (even pixel)
Recommended Supply Voltage
Item
Min.
Typ.
Max. Unit
VDD
11.4
12
12.6
V
Clock Characteristics
Item
Input capacity of φ1∗1, φ2∗1
Input capacity of φLH∗1
Input capacity of φRS∗1
Input capacity of φCLP∗1
Symbol
Cφ1, Cφ2
CφLH
CφRS
CφCLP
Min.
Typ.
Max. Unit
—
400
—
pF
—
10
—
pF
—
10
—
pF
—
10
—
pF
Input capacity of φROG
CφROG
—
10
—
pF
∗1 It indicates that φ1-ODD, φ1-EVEN as φ1, φ2-ODD, φ2-EVEN as φ2, φLH-ODD, φLH-EVEN as φLH, φRS-ODD,
φRS-EVEN as φRS, φCLP-ODD, φCLP-EVEN as φCLP.
Clock Frequency
Item
Symbol
Min.
Typ.
Max. Unit
φ1, φ2, φLH, φRS, φCLP fφ1, fφ2, fφLH, fφRS, fφCLP
—
1
20
MHz
Data rate
fφR
—
2
40
MHz
Input Clock Pulse Voltage Condition
Item
φ1, φ2, φLH, φRS, φCLP, φROG
pulse voltage
High level
Low level
Min.
Typ.
Max. Unit
4.75
5.0
5.25
V
—
0
0.1
V
–2–