AT91SAM9G45-CU Просмотр технического описания (PDF) - Atmel Corporation

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производитель

AT91SAM9G45-CU

AT91SAM ARM-based Embedded MPU

Atmel Corporation 

Doc. Rev

6438D

Comments (Continued)

LCD Controller (LCDC):

Section 45.12.12 “LCD Timing Configuration Register 1”, ‘-’ replaced by ‘1’ for bit 31, and ‘Bit 31 must be

written to 1’ added to VHDLY definition.

Parallel Input/Output Controller (PIO):

- DELAY Registers were addded in a Section 30.4.12 “Programmable I/O Delays” and associated register

description added in a Section 30.6.30 “PIO I/O Delay Register”.

- “Write Protected Registers” description added, together with Section 30.6.31 “PIO Write Protect Mode

Register”and Section 30.6.32 “PIO Write Protect Status Register”.

In Section 30.6.11 “PIO Clear Output Data Register”, “P0-P31: Set Output Data” changed into “P0-P31:

Clear Output Data”

All ‘slewrate’ changed into ‘drive’.

All ‘IO’ changed into ‘I/O’.

All Section 30.6 “Parallel Input/Output Controller (PIO) User Interface” headers now start with ‘PIO’ only.

Any extra ‘Controller’ or ‘Controller PIO’ removed.

Static Memory Controller (SMC):

Table 21-5 removed from Section 21.8.6 “Reset Values of Timing Parameters”. Cross-referenced Table

21-8 instead.

USB Host Port:

Section 37. “USB High Speed Host Port (UHPHS)” , HS (High Speed) was added to the title.

Change

Request

Ref.

6685

6715

6742

6644

Doc. Rev

6438C

Comments

Introduction:

Section 3. “Signal Description” , Table 3-1, in “Reset/Test” description, NRST pin updated with note

concerning NRST configuration.

Section 4. “Package and Pinout”, Table 4-1 updated.

Boot Program:

Section 11.5.2.1 “Supported External Crystal/External Clocks”, ...”supports 12 MHz”...

RSTC:

Section 12.5 “USB High Speed Device Port (UDPHS) User Interface” Table 12-1 Mode register backup

reset value is 0x0000 0001.

Change

Request

Ref.

6600

6639

6598

6639

SAM9G45 [DATASHEET] 1171

6438K–ATARM–12-Feb-13

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