AT91SAM9G45(2009) Просмотр технического описания (PDF) - Atmel Corporation
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AT91SAM9G45 Datasheet PDF : 1159 Pages
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20.2 DDR2 Controller ............................................................................................155
20.3 External Bus Interface (EBI) ..........................................................................160
21 Static Memory Controller (SMC) ......................................................... 183
21.1 Description .....................................................................................................183
21.2 I/O Lines Description .....................................................................................183
21.3 Multiplexed Signals ........................................................................................183
21.4 Application Example ......................................................................................184
21.5 Product Dependencies ..................................................................................184
21.6 External Memory Mapping .............................................................................185
21.7 Connection to External Devices ....................................................................185
21.8 Standard Read and Write Protocols ..............................................................190
21.9 Automatic Wait States ...................................................................................198
21.10 Data Float Wait States ...................................................................................203
21.11 External Wait .................................................................................................207
21.12 Slow Clock Mode ...........................................................................................213
21.13 Asynchronous Page Mode ............................................................................216
21.14 Programmable IO Delays ..............................................................................219
21.15 Static Memory Controller (SMC) User Interface ............................................220
22 DDR/SDR SDRAM Controller (DDRSDRC) ......................................... 227
22.1 Description .....................................................................................................227
22.2 DDRSDRC Module Diagram .........................................................................228
22.3 Product Dependencies ..................................................................................229
22.4 Functional Description ...................................................................................234
22.5 Software Interface/SDRAM Organization, Address Mapping ........................253
22.6 Programmable IO Delays ..............................................................................256
22.7 DDR-SDRAM Controller (DDRSDRC) User Interface ...................................256
23 Error Corrected Code Controller (ECC) ............................................. 275
23.1 Description .....................................................................................................275
23.2 Block Diagram ...............................................................................................275
23.3 Functional Description ...................................................................................275
23.4 Error Corrected Code Controller (ECC) User Interface .................................280
23.5 Registers for 1 ECC for a page of 512/1024/2048/4096 bytes ......................291
23.6 Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes,
8-bit word .......................................................................................................293
23.7 Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes,
8-bit word .......................................................................................................301
iv AT91SAM9G45
6438D–ATARM–13-Oct-09
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