Timing Diagrams (continued)
Pipeline Timing
CLK
tAS
ADD A
B
C
D
tADS
ADSP
tCH
tCYC
tADH
CY7C1325
tCL
E
F
G
H
ADSC
ADV
CE1
tCES
tCEH
CE
WE
OE
ADSP ignored
with CE1 HIGH
tCLZ
Data
tCDV
Q(A) Q(B) Q(C) Q(D)
tWES
Device originally
deselected
tWEH
D (E) D (F) D (G) DD((CH))
tDOH
tCHZ
CE is the combination of CE2 and CE3. All chip selects need to be active in order to select
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
= DON’T CARE
= UNDEFINED
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