CXD1961AQ Просмотр технического описания (PDF) - Sony Semiconductor

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производитель

CXD1961AQ

DVB-S Frontend IC (QPSK demodulation + FEC)

Sony Semiconductor 

CXD1961AQ

Sub address 0B (hex)

Read

CAR_OFST Carrier Capture offset value

OFC7 to OFC0

OFC7: Sign

Offset frequency at the point of carrier capture

(Latest offset frequency is output to register 02 (hex))

(offset frequency) = (Symbol rate) × OFC [7:0] ÷ 1024 (Hz)

Ex.) 20MSPS OFC [6:0] = 11110000 (bin)

(offset freq.)

= 20MHz × (–16) ÷ 1024

= –312.5kHz

Sub address 0C (hex)

Write

MQS/CLK Qsync mode/Clock recovery

MQS3 to MQS0

(MSB) (LSB)

Threshold for carrier lock detection

AK1 to AK0

CE1 to CE0

Clock recovery loop filter coefficient

00: Max. 11: min.

Clock recovery loop filter gain

00: Min. 11: Max.

Clock recovery range is approximately ±200ppm with CE (1:0) = 11.

Sub address 0D (hex)

Write

CODE/SRS Code rate select/Symbol rate select

RATE2 to RATE0

Code rate setting

RATE2

0

0

0

1

1

1

1

RATE1

0

1

1

0

0

1

1

RATE0

1

0

1

0

1

0

1

Code rate R

1/2

2/3

3/4

4/5

5/6

6/7

7/8

SRSAVE

By saving several NCO control word to sub registers initially, symbol rate can be

changed by setting the number of the sub register in which the desired control

word is saved. There are three sub registers.

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