CXD1961AQ Просмотр технического описания (PDF) - Sony Semiconductor

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производитель

CXD1961AQ

DVB-S Frontend IC (QPSK demodulation + FEC)

Sony Semiconductor 

CXD1961AQ

Sub address 07 (hex)

Read

CODE/BER Code rate and BER

RO2 to RO0

Current punctured rate (code rate)

RO2

0

0

0

1

1

1

1

RO1

0

1

1

0

0

1

1

RO0

1

0

1

0

1

0

1

Code rate

1/2

2/3

3/4

4/5

5/6

6/7

7/8

QBER1 to QBER0

4 level BER indicator of QPSK output.

This indicator is valid when QSYNC, VSYNC and FSYNC are all High and

TQBEC [1:0] = 10 (bin). TQBEC [1:0] is in register 11 (hex).

QBER1 QBER0

0

0

0

1

1

0

1

1

Bit Error Rate

more than 10–2

10–3 < ∗ <10–2

10–4 < ∗ <10–3

less than 10–4

VBER1 to VBER0

4 level BER indicator of Viterbi output.

This indicator is valid when QSYNC, VSYNC and FSYNC are all High.

VBER1

0

0

1

1

VBER0

0

1

0

1

Bit Error Rate

more than 10–2

10–3 < ∗ <10–2

10–4 < ∗ <10–3

less than 10–4

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