ADSP-21065L Просмотр технического описания (PDF) - Analog Devices
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ADSP-21065L Datasheet PDF : 44 Pages
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ADSP-21065L
Asynchronous Read/Write—Host to ADSP-21065L
Use these specifications for asynchronous host processor accesses of an ADSP-21065L, after the host has asserted CS and HBR
(low). After the ADSP-21065L returns HBG, the host can drive the RD and WR pins to access the ADSP-21065L’s IOP registers.
HBR and HBG are assumed low for this timing. Writes can occur at a minimum interval of (1/2) tCK.
Parameter
Min
Max
Unit
Read Cycle
Timing Requirements:
tSADRDL
Address Setup/CS Low Before RD Low*
0.0
ns
tHADRDH
Address Hold/CS Hold Low After RD High
0.0
ns
tWRWH
RD/WR High Width
6.0
ns
tDRDHRDY
RD High Delay After REDY (O/D) Disable
0.0
ns
tDRDHRDY
RD High Delay After REDY (A/D) Disable
0.0
ns
Switching Characteristics:
tSDATRDY
tDRDYRDL
Data Valid Before REDY Disable from Low
REDY (O/D) or (A/D) Low Delay After RD Low
tRDYPRD
tHDARWH
REDY (O/D) or (A/D) Low Pulsewidth for Read
Data Disable After RD High
1.5
ns
13.5
ns
28.0 + DT
ns
2.0
10.0
ns
Write Cycle
Timing Requirements:
tSCSWRL
CS Low Setup Before WR Low
0.0
ns
tHCSWRH
CS Low Hold After WR High
0.0
ns
tSADWRH
Address Setup Before WR High
5.0
ns
tHADWRH
Address Hold After WR High
2.0
ns
tWWRL
WR Low Width
7.0
ns
tWRWH
RD/WR High Width
6.0
ns
tDWRHRDY
WR High Delay After REDY (O/D) or (A/D) Disable
0.0
ns
tSDATWH
Data Setup Before WR High
5.0
ns
tHDATWH
Data Hold After WR High
1.0
ns
Switching Characteristics:
tDRDYWRL
REDY (O/D) or (A/D) Low Delay After WR/CS Low
13.5
ns
tRDYPWR
REDY (O/D) or (A/D) Low Pulsewidth for Write
7.75
ns
NOTE
*Not required if RD and address are valid tHBGRCSV after HBG goes low. For first access after HBR asserted, ADDR23-0 must be a nonMMS value 1/2 tCLK before
RD or WR goes low or by tHBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See Host Inter-
face, in the ADSP-21065L SHARC User’s Manual, Second Edition.
–24–
REV. C
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