74LVX132TTR(2004) Просмотр технического описания (PDF) - STMicroelectronics

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74LVX132TTR
(Rev.:2004)

LOW VOLTAGE CMOS QUAD 2-INPUT SCHMITT NAND GATE WITH 5V TOLERANT INPUTS

STMicroelectronics 

74LVX132

LOW VOLTAGE CMOS QUAD 2-INPUT SCHMITT NAND GATE

WITH 5V TOLERANT INPUTS

s HIGH SPEED:

tPD = 5.9ns (TYP.) at VCC = 3.3V

s 5V TOLERANT INPUTS

s LOW POWER DISSIPATION:

ICC = 2 µA (MAX.) at TA=25°C

) s TYPICAL HYSTERESIS: 0.7V at VCC = 3.3V

t(s s LOW NOISE:

c VOLP = 0.3V (TYP.) at VCC = 3.3V

u s SYMMETRICAL OUTPUT IMPEDANCE:

d |IOH| = IOL = 4mA (MIN)

ro s BALANCED PROPAGATION DELAYS:

P tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

te VCC(OPR) = 2V to 3.6V (1.2V Data Retention)

le s PIN AND FUNCTION COMPATIBLE WITH

o 74 SERIES 132

bs s IMPROVED LATCH-UP IMMUNITY

s POWER DOWN PROTECTION ON INPUTS

) - O DESCRIPTION

t(s The 74LVX132 is a low voltage CMOS QUAD

2-INPUT SCHMITT NAND GATE fabricated with

c sub-micron silicon gate and double-layer metal

du wiring C2MOS technology. It is ideal for low

ro power, battery operated and low noise 3.3V

applications. Power down protection is provided

P on all inputs and 0 to 7V can be accepted on

te inputs with no regard to the supply voltage.

SOP

TSSOP

Table 1: Order Codes

PACKAGE

SOP

TSSOP

T&R

74LVX132MTR

74LVX132TTR

This device can be used to interface 5V to 3V

system. It combines high speed performance with

the true CMOS low power consumption.

Pin configuration and function are the same as

those of the 74LVX00 but the 74LVX132 has

hysteresis.

This together with its schmitt trigger function

allows it to be used on line receivers with slow

rise/fall input signals.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

Obsole Figure 1: Pin Connection And IEC Logic Symbols

August 2004

Rev. 3

1/11

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