PRELIMINARY
KL5KUSB121
4.2 SRAM Write Access
USB to 10/100 Ethernet Controller
Figure 4.2.1 SRAM Write AC Timing
SRAMA14-0
(OUT)
Twc
valid
Tdaw
SRAMOEN
(OUT)
SRAMCSN
(OUT)
SRAMWEN
(OUT)
Tdrv
SRAMD7-0
(OUT)
Tdcw
Tpwe
Tval
valid
Tdwa
Tdwc
Tts
Table 4.2.1 SRAM Write AC Characteristics (over recommended range)
Symbol
Parameter
Min Typ Max Unit Not
e
Twc
SRAM write cycle
31.25 –
– ns 1,2
Fwc
SRAM write frequency –
–
32 MH 1,2
z
Tdaw SRAMWEN assert
delay
0
–
– ns 2
from SRAMA valid
Tdwa SRAMA invalid delay
from SRAMWEN
0
–
– ns 2
negate
Tdcw SRAMWEN assert
delay
0
–
– ns 2
from SRAMCSN assert
Tdwc SRAMCSN negate
delay
0
–
– ns 2
from SRAMWEN
negate
Tpwe SRAMWEN low width 25
–
– ns 2
Tdrv
SRAMD drive delay
from SRAMWEN
0
–
– ns 2
assert
Tval
SRAMD valid
from SRAMWEN
–
–
15 ns 2
assert
Tts
SRAMD hold time
from SRAMWEN rise
0
–
– ns 2
Note: 1) Same as the USB to Ethernet internal clock cycle time 1T (31.25 ns).
2) Outputs are assumed to have 30pF external capacitive load.
Ver. 1.1
Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com
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