KL5KUSB121_L Просмотр технического описания (PDF) - KAWASAKI MICROELECTRONICS

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KL5KUSB121_L

USB to 10/100 Ethernet Controller

KAWASAKI MICROELECTRONICS 

4. SRAM Interface

4.1 SRAM Read Access

PRELIMINARY

KL5KUSB121

USB to 10/100 Ethernet Controller

Figure 4.1.1 SRAM Read AC Timing

SRAMA14-0

(OUT)

SRAMWEN

(OUT)

SRAMOEN

(OUT)

SRAMCSN

(OUT)

SRAMD7-0

(IN)

Trc

valid

Taa

Thad

Tpoe

Toe

Tpcs

Thoe

Tacs

don't care

Thcs

valid

Table 4.1.1 SRAM Read AC Characteristics (over recommended range)

Symbol

Parameter

Min Typ Max Unit Not

e

Trc

SRAM read cycle

31.25 –

– ns 1,2

Frc

SRAM read frequency –

–

32 MH 1,2

z

Taa

SRAMA valid to

SRAMD

–

–

17 ns 2

delay (address access)

Thad SRAMD hold time from

SRAMD invalid

2

–

– ns 2

Tpoe SRAMOEN low width 31.25 –

– ns 2

Toe

SRAMOEN assert to

SRAMD delay

–

–

10 ns 2

Thoe SRAMD hold time

from SRAMOEN rise

0

–

– ns 2

Tpcs SRAMCSN low width 31.25 –

– ns 1,2

Tacs SRAMCSN assert to

SRAMD delay

–

–

17 ns 2

Thcs SRAMD hold time

from SRAMCSN rise

0

–

– ns 2

Note: 1) Same as the USB to Ethernet internal clock cycle time 1T (31.25 ns).

2) Outputs are assumed to have 30pF external capacitive load.

Ver. 1.1

Kawasaki LSI • 2570 North First Street • Suite 301 • San Jose, CA 95131 • Tel: (408) 570-0555 • Fax: (408) 570-0567 • www.klsi.com

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