CXA3246Q Просмотр технического описания (PDF) - Sony Semiconductor
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CXA3246Q Datasheet PDF : 22 Pages
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CXA3246Q
Electrical Characteristics
(AVCC, DVCC1, 2, DGND3 = +5V, AGND, DGND1, 2, DVEE3 = 0V, VRT = 4V, VRB = 2V, Ta = 25°C)
Item
Symbol
Conditions
Min.
Typ. Max. Unit
Resolution
8
bits
DC characteristics
Integral linearity error
EIL
Differential linearity error EDL
VIN = 2Vp-p, Fc = 5MSPS
±0.5 LSB
±0.5 LSB
Analog input
Analog input capacitance CIN
Analog input resistance RIN
Analog input current
IIN
VIN = +3.0V + 0.07Vrms
10
pF
7
20
40
kΩ
0
100
285
µA
Reference input
Reference resistance
Reference current
Offset voltage VRT side
VRB side
Rref∗2
Iref∗3
EOT
EOB
400
600
740
Ω
2.7
3.3
5.0
mA
6
8
10
mV
0
1.5
3
mV
Digital input (ECL, PECL)
Digital input voltage: High VIH
: Low VIL
Threshold voltage
VTH
Digital input current : High IIH
: Low IIL
Digital input capacitance
VIH = DGND3 – 0.8V
VIL = DGND3 – 1.6V
DVEE3 + 1.5
DGND3 V
DVEE3 + 1.1
VIH – 0.4 V
DGND3 – 1.2
V
–50
20
µA
–50
20
µA
5
pF
Digital input (TTL)
Digital input voltage: High VIH
: Low VIL
Threshold voltage
VTH
Digital input current : High IIH
: Low IIL
Digital input capacitance
VIH = 3.5V
VIL = 0.2V
2.0
1.5
–10
–20
V
0.8
V
V
5
µA
0
µA
5
pF
Digital output (TTL)
Digital output voltage : High VOH
: Low VOL
IOH = –2mA
IOL = 1mA
2.4
0.5
Switching characteristics
Maximum conversion rate Fc
DMUX mode
120
Aperture jitter
Taj
10
Sampling delay
Tds
1.2
1.4
1.6
Clock high pulse width
Tpw1 CLK
3.0
Clock low pulse width
Tpw0 CLK
4.5
Reset signal setup time T_rs
RESETN – CLK
1.0
Reset signal hold time
T_rh
RESETN – CLK
–0.5
Clock output delay
Data output delay
Td_clk
(CL = 5pF) 3.0
4.5
7.0
Tdo1
DMUX mode (CL = 5pF)
T∗4 + 0.5
Tdo2
(CL = 5pF) 3.5
5.0
7.5
Output rise time
Tr
0.8 to 2.0V
(CL = 5pF)
1
Output fall time
Tf
0.8 to 2.0V
(CL = 5pF)
1
∗ These characteristics are for PECL input unless otherwise specified.
V
V
MSPS
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–8–
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