MTL001 Просмотр технического описания (PDF) - Myson Century Inc

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производитель

MTL001

XGA Flat Panel Controller

Myson Century Inc 

MYSON

TECHNOLOGY

MTL001

(Rev. 0.95)

3.4 Memory Interface

General Description

In frame buffer mode, the MTL001 connects to the external frame buffers by means of memory interface. The

external frame memory can be made for 1M516bits SDRAM, 256K532bits or 512K532bits SGRAM

devices. Due to different applications such as VGA, SVGA, XGA as well as SXGA, the image resolution of

input and output will be limited resulting from the bandwidth of memory interface. Two configurations with 24,

32 and 48 bits bus modes will be supported to resolve the bandwidth constraint in most of applications. The

clock for external frame memory devices can be provided from the internal PLL circuit or the external clock

applied to pin EXTMCLK and its frequency can be up to 118 MHz. The MTL001 also supplies a simple and

complete memory self-testing mechanism for SDRAM and SGRAM, which can be used to detect memory cell

status and to check connection in memory interface.

3.4.1 SDRAM Configuration

In current applications, the most popular arrangement of SDRAM is 1M516bits. To achieve the desired

bandwidth in memory interface, 2 or 3 devices are constructed in parallel. The memory clock ranging from

50MHz to 118MHz is tuned by giving appropriate parameters for the internal PLL circuit. In two devices

configuration, the 24 and 32 bits bus modes are supported. In three devices, the 48 bits bus mode is

supported. In 24 bits bus mode, the maximum supported input image resolution is up to 10245768 @ 60Hz.

In 32 and 48 bits bus mode, the maximum supported input image resolution is up to 10245768 @ 85Hz.

Table 3.4.1 gives the configuration for different input and output image format. Figure 3.4.1 shows the

connection between the MTL001 and SDRAM devices in 2 configurations.

Output Resolution

Input Resolution

YUV

VGA (6405480)

SVGA (8005600)

XGA (10245768)

SVGA

2

2

2

2

Unit: device

XGA

2

2

2

2

Table 3.4.1 SDRAM configuration in different input and output modes

3.4.2 SGRAM Configuration

The SGRAM devices in 256K532bits and 512K532bits constructions are usually used to feature the wide

data bus for high speed applications. In case of SGRAM usage, the 32 bits data bus of each device is divided

into 2 parts to store input image data. The memory clock is adjustable to achieve the desired range of

performance like the SDRAM case above. The maximum supported input image resolution in 24 bits bus

mode (2 devices) is up to 8005600 @ 85Hz, and both the 32 bits bus mode (2 devices) and the 48 bits bus

mode (3 devices) can support maximum input image resolution up to 10245768 @ 85Hz. Table 3.4.2

provides the configuration for different input and output image format. Figure 3.4.2 and 3.4.3 show the

connection between the MTL001 and SGRAM devices in 2 configurations by 256K532bits and 512K532bits

constructions respectively.

Output Resolution

Input Resolution

YUV

VGA (6405480)

SVGA (8005600)

XGA (10245768)

(512Kx32 bits / 256Kx32 bits)

SVGA

2

2

2

2/3

Unit: device

XGA

2

2

2

2/3

Table 3.4.2 SGRAM configurations in different input and output modes

Revision 0.95

- 13 -

2000/06/14

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