ADP3510ARU Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге

Компоненты Описание

производитель

ADP3510ARU

CDMA Power Management System

Analog Devices 

ADP3510

To ensure proper operation, the minimum VGS the ADP3510

can provide must be enough to turn on the FET. The available

gate drive voltage can be estimated using the following:

VGS = VADAPTER( MIN ) - VSENSE - VGATEDR

(11)

where:

VADAPTER(MIN) is the minimum adapter voltage.

VDIODE is the maximum forward drop of the charger diode, D1.

VGATEDR is the gate drive “low” voltage, 0.5 V.

VSENSE is the maximum high current limit threshold voltage.

The difference between the adapter voltage (VADAPTER) and the

final battery voltage (VBAT) must exceed the voltage drop due to

the blocking diode, the sense resistor, and the ON resistance of

the FET at maximum charge current.

VDS = VADAPTER( MIN ) - VDIODE - VSENSE - VBAT

(12)

Then the RDS(ON) of the FET can be calculated.

RDS(ON )

=

VDS

ICHR( MAX )

(13)

The thermal characteristics of the FET must be considered

next. The worst-case dissipation can be determined using:

( ) PDISS = VADAPTER( MAX ) - VDIODE - VSENSE - UVLO ¥ ICHR

It should be noted that the adapter voltage can be either preregulated

or nonregulated. In the preregulated case, the difference between

the maximum and minimum adapter voltage is probably not sig-

nificant. In the unregulated case, the adapter voltage can have a

wide range specified. However, the maximum voltage specified is

usually with no load applied. So, the worst-case power dissipation

calculation will often lead to an over-specified pass device. In

either case, it is best to determine the load characteristics of the

adapter to optimize the charger design.

For example:

VADAPTER(MIN) = 5.0 V

VADAPTER(MAX) = 6.5 V

VDIODE = 0.5 V at 850 mA

(14)

VGATEDR = 0.5 V

VSENSE = 170 mV

VGS = 5 V – 0.5 V – 0.170 V = 4.3 V.

So choose a low-threshold voltage FET.

VDS = VADAPTER( MIN ) - VDIODE - VSENSE - VBAT

= 5 V – 0.5 V – 0.170 V – 4.2 V

= 130 mV

(15)

RDS(ON )

=

VDS

ICHR( MAX )

=

130 mV

850 mV

(16)

= 153 mW

( ) PDISS = VADAPTER( MAX ) - VDIODE - VSENSE - UVLO ¥ ICHR

( ) PDISS = 6.5V - 0.5V - 0.170 V - 3.2 ¥ 0 / 85A = 2.24 W

Appropriate PMOS FETs are available from the following vendors:

Siliconix

IR

Fairchild

Charger Diode Selection

The diode, D1, shown in Figure 3, is used to prevent the battery

from discharging through the PMOS’ body diode into the charger’s

internal bias circuits. A Schottky diode is recommended to

minimize the voltage difference from the charger to the battery

and the power dissipation. Choose a diode with a current rating

high enough to handle the battery charging current, a voltage

rating greater than VBAT, and a low leakage current. The blocking

diode is required for both lithium and nickel battery types.

Printed Circuit Board Layout Considerations

Use the following general guidelines when designing printed

circuit boards:

1. Connect the battery to the VBAT and VBAT2 pins of the

ADP3510. Locate the input capacitor as close to the pins as

possible.

2. VAN and VTCXO capacitors should be returned to AGND.

3. VCORE, VMEM, and VIO capacitors should be returned to

DGND.

4. Split the ground connections. Use separate traces or planes for

the analog, digital, and power grounds and tie them together

at a single point, preferably close to the battery return.

5. Run a separate trace from the BATSNS pin to the battery to

prevent voltage drop error in the MVBAT measurement.

6. Kelvin connect the charger’s sense resistor by running separate

traces to the CHRIN pin and ISENSE pin. Make sure that the

traces are terminated as close to the resistor’s body as possible.

7. Use the best industry practice for thermal considerations during

the layout of the ADP3510 and charger components. Careful

use of copper area, weight, and multilayer construction all

contribute to improved thermal performance.

REV. 0

–15–

Share Link: