UPSD3212A(2009) Просмотр технического описания (PDF) - STMicroelectronics

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производитель

UPSD3212A
(Rev.:2009)

Flash programmable system devices with 8032 MCU and USB and programmable logic

STMicroelectronics 

Architecture overview

2

Architecture overview

UPSD3212A, UPSD3212C, UPSD3212CV

2.1

Memory organization

The UPSD321xx devices’ standard 8032 Core has separate 64-Kbyte address spaces for

Program memory and Data Memory. Program memory is where the 8032 executes

instructions from. Data memory is used to hold data variables. Flash memory can be

mapped in either program or data space. The Flash memory consists of two Flash memory

blocks: the main Flash memory (512 Kbit) and the Secondary Flash memory (128 Kbit).

Except during flash memory programming or update, Flash memory can only be read, not

written to. A Page Register is used to access memory beyond the 64-Kbyte address space.

Refer to the PSD module for details on mapping of the Flash memory.

The 8032 core has two types of data memory (internal and external) that can be read and

written. The internal SRAM consists of 256 bytes, and includes the stack area.

The SFR (Special Function Registers) occupies the upper 128 bytes of the internal SRAM,

the registers can be accessed by Direct addressing only. Another 2 Kbytes resides in the

PSD module that can be mapped to any address space defined by the user.

Figure 4. Memory map and address space

MAIN

FLASH

EXT. RAM

SECONDARY

FLASH

64KB

16KB

Flash Memory Space

INT. RAM

FF

Indirect

Addressing

SFR

Direct

Addressing

7F

Indirect

or

Direct

Addressing

0

Internal RAM Space

(256 Bytes)

2KB

External RAM Space

(MOVX)

AI07425

2.2

Registers

The 8032 has several registers; these are the Program Counter (PC), Accumulator (A), B

Register (B), the Stack Pointer (SP), the Program Status Word (PSW), General purpose

registers (R0 to R7), and DPTR (Data Pointer register).

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