DS2155 Просмотр технического описания (PDF) - Maxim Integrated

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DS2155

T1/E1/J1 Single-Chip Transceiver

Maxim Integrated 

Figure 37-8. Receive-Side Timing

RCLK

tD1

RSER / RDATA / RSIG

RSYNC 1

RFSYNC / RMSYNC

RCHCLK

RCHBLK

RLCLK 2

RLINK (T1MODE)

RLINK (E1 MODE)4

1ST FRAME BIT

tD2

tD2

t D2

tD2

tD2

tD1

Sa4 to Sa8

Bit Position

Note 1: RSYNC is in the output mode.

Note 2: Shown is RLINK/RLCLK in the ESF framing mode.

Note 3: No relationship between RCHCLK and RCHBLK and other signals is implied.

Note 4: RLCLK only pulses high during Sa bit locations as defined in the E1RCR2 register.

DS2155

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