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DSP1627
(Rev.:2000)

DSP1627 Digital Signal Processor

Agere -> LSI Corporation 

DSP1627 Digital Signal Processor

Data Sheet

March 2000

4 Hardware Architecture (continued)

For additional power savings, set ioc = 0x0180 and tim-

erc = 0x0040 in addition to setting alf = 0x8000. This will

hold the CKO pin low and shut down the timer and pres-

caler (see Table 38 and Table 31).

For a description of the control mechanisms for putting

the DSP into low-power modes, see Section 4.13, Pow-

er Management.

4.4 Memory Maps and Wait-States

The DSP1600 core implements a modified Harvard ar-

chitecture that has separate on-chip 16-bit address and

data buses for the instruction/coefficient (X) and data

(Y) memory spaces. Table 5 shows the instruction/coef-

ficient memory space maps for both the DSP1627x36

and DSP1627x32.

The differences between the x36 and x32 memory

maps can be seen by comparing the respective MAP1

and MAP3. For instance, MAP1 of the x36 provides for

36 Kwords of IROM and 6 Kwords of dual-port RAM

(DPRAM), whereas MAP1 of the x32 provides for

32 Kwords of IROM, 6 Kwords of DPRAM, and

16 Kwords of EROM.

The DSP1627 provides a multiplexed external bus

which accesses external RAM (ERAM) and ROM (ER-

OM). Programmable wait-states are provided for exter-

nal memory accesses. The instruction/coefficient

memory map is configurable to provide application flex-

ibility. Table 6 shows the data memory space, which

has one map.

Instruction/Coefficient Memory Map Selection

In determining which memory map to use, the proces-

sor evaluates the state of two parameters. The first is

the LOWPR bit (bit 14) of the alf register. The LOWPR

bit of the alf register is initialized to 0 automatically at re-

set. LOWPR controls the starting address in memory

assigned to the six 1K banks of dual-port RAM. If LOW-

PR is low, internal dual-port RAM begins at address

0xC000. If LOWPR is high, internal dual-port RAM be-

gins at address 0x0. LOWPR also moves IROM from

0x0 in MAP1 to 0x4000 in MAP3, and EROM from 0x0

in MAP2 to 0x4000 in MAP4.

The second parameter is the value at reset of the EXM

pin (pin 27 or pin 14, depending upon the package

type). EXM determines whether the internal 36 Kwords

ROM (IROM) will be addressable in the memory map.

The Lucent Technologies development system tools,

together with the on-chip HDS circuitry and the JTAG

port, can independently set the memory map. Specifi-

cally, during an HDS trap, the memory map is forced to

16

MAP1. The user's map selection is restored when the

trap service routine has completed execution.

MAP1

MAP1 has the IROM starting at 0x0 and six 1 Kword

banks of DPRAM starting at 0xC000. Additionally,

MAP1 for the x32 has 16 Kwords of EROM starting at

0x8000. MAP1 is used if DSP1627 has EXM low at re-

set and the LOWPR parameter is programmed to zero.

It is also used during an HDS trap.

MAP2

MAP2 differs from MAP1 in that the lowest 48 Kwords

reference external ROM (EROM). MAP2 is used if EXM

is high at reset, the LOWPR parameter is programmed

to zero, and an HDS trap is not in progress.

MAP3

MAP3 has the six 1 Kword banks of DPRAM starting at

address 0x0. In MAP3 of the x36, the 36 Kwords of

IROM start at 0x4000. Similarly, for the x32, 32 Kwords

of IROM start at 0x4000. Additionally, MAP3 for the x32

has 16 Kwords of EROM starting at 0xC000. MAP3 is

used if EXM is low at reset, the LOWPR bit is pro-

grammed to 1, and an HDS trap is not in progress. Note

that this map is not available if the secure mask-pro-

grammable option has been ordered.

MAP4

MAP4 differs from MAP3 in that addresses above

0x4000 reference external ROM (EROM). This map is

used if the LOWPR bit is programmed to 1, an HDS trap

is not in progress, and, either EXM is high during reset,

or the secure mask-programmable option has been or-

dered.

Whenever the chip is reset using the RSTB pin, the de-

fault memory map will be MAP1 or MAP2, depending

upon the state of the EXM pin at reset. A reset through

the HDS will not reinitialize the alf register, so the previ-

ous memory map is retained.

Boot from External ROM

After RSTB goes from low to high, the DSP1627 comes

out of reset and fetches an instruction from address

zero of the instruction/coefficient space. The physical

location of address zero is determined by the memory

map in effect. If EXM is high at the rising edge of RSTB,

MAP2 is selected. MAP2 has EROM at location zero;

thus, program execution begins from external memory.

If EXM is high and INT1 is low when RSTB rises, the

mwait register defaults to 15 wait-states for all external

memory segments. If INT1 is high, the mwait register

defaults to 0 wait-states.

Lucent Technologies Inc.

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