MB86941 Просмотр технического описания (PDF) - Fujitsu

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Компоненты Описание

производитель

MB86941

Peripheral LSI for SPARClite

Fujitsu 

MB86941/942

6. I/O PORT SIGNALS (16)

Pin symbol I/O Pin no.

Pin name

IPD0

I/O 72 I/O Port 0

IPD1

I/O 78 I/O Port 1

IPD2

I/O 84 I/O Port 2

IPD3

I/O 85 I/O Port 3

IPD4

I/O 86 I/O Port 4

IPD5

I/O 87 I/O Port 5

IPD6

I/O 94 I/O Port 6

IPD7

I/O 95 I/O Port 7

IPD8

I/O 96 I/O Port 8

IPD9

I/O 98 I/O Port 9

IPD10

I/O 99 I/O Port 10

IPD11

I/O 103 I/O Port 11

IPD12

I/O 104 I/O Port 12

IPD13

I/O 105 I/O Port 13

IPD14

I/O 106 I/O Port 14

IPD15

I/O 107 I/O Port 15

7. SIO SIGNALS (4)

Pin symbol I/O Pin no.

Pin name

SICLK

I/O 114 SIO Clock

SIRXD

SITXD

SIIRQ

I 109 SIO Receive Data

O 110 SIO Transmit Data

O 111 SIO Interrupt Request

Description

Signal I/O port

These pins may be used for input or output, as

determined by register setting.

These pins have internal pull-up resistance (MB86941

only).

Description

This is the input/output pin for the clock signal used for

SIO serial data transfer.

In external clock mode, the clock signal for serial data

transfer is input at this pin.

In internal clock mode, the clock signal from the

internal clock generator is output at this pin.

This pin has internal pull-up resistance (MB86941

only).

SIO Receive Data input pin

This pin receives data input LSB first, synchronously

with the SICLK pin clock signal. This pin has internal

pull-up resistance (MB86941 only).

SIO Transmit Data output pin

This pin outputs data LSB first, synchronously with the

SICLK pin clock signal.

SIO Interrupt Request output pin

15

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