AN4506 Просмотр технического описания (PDF) - STMicroelectronics

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AN4506

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AN4506

First-in first-out (FIFO) buffer

The interrupt trigger is related to the IA bit in the IG_SRC register and it is generated even if

the interrupt signal is not driven to an interrupt pad. Bypass-to-Stream mode is sensitive to

the trigger level and not to the trigger edge; this means that if the FIFO buffer is in Stream

mode and the interrupt condition disappears, the FIFO buffer returns to Bypass mode

because the IA bit becomes zero.

It is recommended to latch the interrupt signal used as the stream trigger in order to avoid

losing interrupt events. If the selected interrupt is latched, it is necessary to read the register

IG_SRC to clear the IA bit; after reading, the IA bit takes 2*ODR to go low.

In Stream mode the FIFO buffer continues filling. When the buffer is full, the OVRN bit is set

high and the next samples overwrite the oldest.

Figure 27. Bypass-to-Stream mode

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Bypass-to-Stream can be used in order to start the acquisition when the configured interrupt

is generated.

Bypass-to-FIFO mode

This mode is a combination of the Bypass and FIFO modes previously described: the FIFO

buffer starts operating in Bypass mode and switches to FIFO mode when an interrupt

occurs.

Follow these steps for Bypass-to-FIFO mode configuration:

1. Configure the desired interrupt generator by using register IG_CFG (0x30).

2. Turn on FIFO by setting the FIFO_En bit to “1” in the CTRL5 register (0x24). After this

operation the FIFO buffer is enabled but is not collecting data, output registers are

frozen to the last samples set loaded.

3. Activate Bypass-to-FIFO mode by setting the FM[2:0] field to “111” in the FIFO_CTRL

register (0x2E).

The interrupt trigger is related to the IA bit in the IG_SRC register and it is generated even if

the interrupt signal is not driven to an interrupt pad.

It is recommended to latch the interrupt signal used as the stream trigger in order to avoid

losing interrupt events. If the selected interrupt is latched, it is necessary to read the register

IG_SRC to clear the IA bit; after reading, the IA bit takes 2*ODR to go low.

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