AN4506 Просмотр технического описания (PDF) - STMicroelectronics

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AN4506

L3GD20H: 3-axis digital output gyroscope

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First-in first-out (FIFO) buffer

Figure 18. FIFO_EN connection block diagram

AN4506

6.2.2

FIFO control register (0x2E)

This register is dedicated to FIFO mode selection and FIFO threshold configuration.

Table 30. FIFO_CTRL register

b7

b6

b5

b4

b3

b2

b1

b0

FM2

FM1

FM0

FTH4

FTH3

FTH2

FTH1

FTH0

FM[2:0] bits are dedicated to define the FIFO buffer behavior selection:

1. FM[2:0] = (0,0,0): Bypass mode

2. FM[2:0] = (0,0,1): FIFO mode

3. FM[2:0] = (0,1,0): Stream mode

4. FM[2:0] = (0,1,1): Stream-to-FIFO mode

5. FM[2:0] = (1,0,0): Bypass-to-Stream mode

6. FM[2:0] = (1,1,0): Dynamic Stream mode

7. FM[2:0] = (1,1,1): Bypass-to-FIFO mode

The trigger used to activate Stream-to-FIFO and Bypass-to-Stream modes is related to the

IA bit value of the selected IG_SRC register and does not depend on the interrupt pin value

and polarity. The trigger is generated even if the selected interrupt is not driven to an

interrupt pin.

FTH[4:0] bits are intended to define the FIFO threshold level; when FIFO content exceeds

this value, the FTH bit is set to “1” in the FIFO source register.

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