3. DRAM Interface (Output Load = 30pF)
(1) Read
iCLK
MA9 to 0
Tma0
Tma1
XRAS
Trasl
XUCAS
XLCAS
XMWR
MDBF to 0
Trc
Trash
Tcasl
Tcash
Tmdrh
Tmdrs
Item
Random read/write cycle time
Address delay time (for XTL2 ↑)
Address delay time (for XTL2 ↑)
XRAS ↓ delay time (for XTL2 ↑)
XRAS ↑ delay time (for XTL2 ↑)
XCAS ↓ delay time (for XTL2 ↑)
XCAS ↑ delay time (for XTL2 ↑)
Data setup time (for XTL2 ↑)
Data hold time (for XCAS ↑)
Symbol Min. Typ. Max. Unit
Trc
5Tw
ns
Tma0
13
24
45
ns
Tma1
11
22
41
ns
Trasl
6
12
23
ns
Trash
6
11
20
ns
Tcasl
7
14
25
ns
Tcash
6
12
22
ns
Tmdrs
2
4
6
ns
Tmdrh
0
ns
CXD1804BR
"H"
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