W77E468 Просмотр технического описания (PDF) - Winbond
Номер в каталоге
Компоненты Описание
производитель
W77E468 Datasheet PDF : 84 Pages
| |||
Preliminary W77E468
TIMER CONTROL
Bit:
7
6
5
4
3
2
1
0
TF1 TR1 TF0 TR0 IE1
IT1
IE0
IT0
Mnemonic: TCON
Address: 88h
TF1:
TR1:
TF0:
TR0:
IE1:
IT1:
IE0:
IT0:
Timer 1 overflow flag: This bit is set when Timer 1 overflows. It is cleared automatically when
the program does a timer 1 interrupt service routine. Software can also set or clear this bit.
Timer 1 run control: This bit is set or cleared by software to turn timer/counter on or off.
Timer 0 overflow flag: This bit is set when Timer 0 overflows. It is cleared automatically when
the program does a timer 0 interrupt service routine. Software can also set or clear this bit.
Timer 0 run control: This bit is set or cleared by software to turn timer/counter on or off.
Interrupt 1 edge detect: Set by hardware when an edge/level is detected on INT1 . This bit is
cleared by hardware when the service routine is vectored to only if the interrupt was edge
triggered. Otherwise it follows the pin.
Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level triggered
external inputs.
Interrupt 0 edge detect: Set by hardware when an edge/level is detected on INT0 . This bit is
cleared by hardware when the service routine is vectored to only if the interrupt was edge
triggered. Otherwise it follows the pin.
Interrupt 0 type control: Set/cleared by software to specify falling edge/ low level triggered
external inputs.
TIMER MODE CONTROL
Bit:
7
6
5
4
3
2
1
0
GATE C/ T
M1
M0 GATE C/ T
M1
M0
Mnemonic: TMOD
TIMER1
TIMER0
Address: 89h
GATE: Gating control: When this bit is set, Timer/counter x is enabled only while INTx pin is high
and TRx control bit is set. When cleared, Timer x is enabled whenever TRx control bit is set.
C/ T : Timer or Counter Select: When cleared, the timer is incremented by internal clocks. When
set, the timer counts high-to-low edges of the Tx pin.
- 14 -
Share Link: 