KSZ8051MNLV-TR Просмотр технического описания (PDF) - Microchip Technology
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KSZ8051MNLV-TR Datasheet PDF : 66 Pages
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KSZ8051MNL/RNL
3.2.1 MII SIGNAL DEFINITION
Table 3-1 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.
TABLE 3-1: MII SIGNAL DEFINITION
MII Signal
Name
TXC
TXEN
TXD[3:0]
RXC
RXDV
RXD[3:0]
RXER
CRS
COL
Direction with
Respect to PHY,
KSZ8051MNL
Signal
Output
Input
Input
Output
Output
Output
Output
Output
Output
Direction with
Respect to MAC
Description
Input
Transmit Clock
(2.5 MHz for 10 Mbps; 25 MHz for 100 Mbps)
Output
Transmit Enable
Output
Transmit Data[3:0]
Input
Receive Clock
(2.5 MHz for 10 Mbps; 25 MHz for 100 Mbps)
Input
Receive Data Valid
Input
Receive Data[3:0]
Input or not required Receive Error
Input
Carrier Sense
Input
Collision Detection
3.2.1.1 Transmit Clock (TXC)
TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN, TXD[3:0], and TXER.
TXC is 2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation.
3.2.1.2 Transmit Enable (TXEN)
TXEN indicates that the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the
first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII. It is
negated before the first TXC following the final nibble of a frame.
TXEN transitions synchronously with respect to TXC.
3.2.1.3 Transmit Data[3:0] (TXD[3:0])
TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, TXD[3:0] are accepted by the PHY
for transmission. TXD[3:0] is 00 to indicate idle when TXEN is de-asserted. Values other than 00 on TXD[3:0] while
TXEN is de-asserted are ignored by the PHY.
3.2.1.4 Receive Clock (RXC)
RXC provides the timing reference for RXDV, RXD[3:0], and RXER.
In 10 Mbps mode, RXC is recovered from the line while the carrier is active. When the line is idle or the link is down,
RXC is derived from the PHY’s reference clock.
In 100 Mbps mode, RXC is continuously recovered from the line. If the link is down, RXC is derived from the PHY’s
reference clock.
RXC is 2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation.
3.2.1.5 Receive Data Valid (RXDV)
RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0].
In 10 Mbps mode, RXDV is asserted with the first nibble of the start-of-frame delimiter (SFD), 5D, and remains asserted
until the end of the frame.
In 100 Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame.
RXDV transitions synchronously with respect to RXC.
DS00002310A-page 18
2016 Microchip Technology Inc.
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