CXP84332M/84340M
Pin
PE4/PWM
1 pin
Port E
Circuit format
PWM
Port E output
selection
"0" when reset
Port E data
"1" when reset
Data bus
RD (Port E)
Port E
When reset
High level
PE5/TO/ADJ
1 pin
PD0 to PD7
PF0 to PF7
PG0 to PG7
PH0 to PH7
PI4 to PI7
36 pins
Output enable
TO
ADJ16K
ADJ2K
Port E output
selection
Port E output
selection
"00" when reset
Port E output
selection
"0" when reset
MPX
Port E data
"1" when reset
Data bus
RD (Port E)
∗ ADJ signals are frequency dividing outputs
for 32kHz oscillation frequency adjustment
ADJ2K provides usage as buzzer output.
Port D
Port F
Port G
Pull-up resistance
∗
Port H
"0" when reset
Port I
Ports D, F, G, H, I data
Ports D, F, G, H, I directon
"0" when reset
Data bus
RD (Ports D, F, G, H, I)
IP
∗ Pull-up transistors
approx. 10kΩ
High level
Hi-Z
–8–