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SI5332F

6/8/12-Output Any-Frequency Clock Generator

Silicon Laboratories 

Si5332 Data Sheet

Functional Description

3.4 Inputs

The Si5332 requires an external 16–30 MHz crystal at its XIN/XOUT pins or the embedded 50 MHz crystal to operate in free-run mode,

or an external input clock (CLKIN_2/CLKIN_2# or CLKIN_3/CLKIN_3#) for synchronous operation. An external crystal is not required in

synchronous mode.

3.4.1 External Reference Input (XA/XB)

An external crystal (XTAL) is used in combination with the internal oscillator (OSC) on Si5332A/B/C/D to produce a low jitter reference

for the PLL when operating in the free-run mode. Frequency offsets due to CL mismatch can be adjusted using the frequency adjust-

ment feature which allows frequency adjustments of ±1000 ppm. The Si5332 Reference Manual provides additional information on PCB

layout recommendations for the crystal to ensure optimum jitter performance. Refer to Table 5.4 External Crystal Input Specification on

page 24 for crystal specifications.

For free-running operation, the internal oscillator can operate from a low-frequency fundamental mode crystal (XTAL) with a resonant

frequency of 16 to 50 MHz. A crystal can easily be connected to pins XA and XB without external components, as shown in the figure

below. A register bit will allow the device to use an internal loading capacitor (CL) with a typical value of 12 pF or bypass the internal CL

and use external CL. Alternatively, an external CL can be used along with the internal CL.

XA

XTAL

Osc

To synthesis stage

or output selectors

XB

Figure 3.4. External Reference Input (XA/XB)

The Si5332E/F/G/H options feature an embedded 50 MHz reference crystal that is used in the free run mode.

3.4.2 Input Clocks

An input clock is available to synchronize the PLL when operating in synchronous mode. This input can be configured as LVPECL,

LVDS or HCSL differential, or LVCMOS. The recommended input termination schemes are shown in the Si5332 Family Reference

Manual. Differential signals must be AC coupled. The single-ended LVCMOS input is internally AC coupled, and only needs to meet a

minimum voltage swing that may not exceed a maximum VIH or minimum VIL. Unused inputs can be disabled by register configuration.

3.4.3 Input Selection

The active clock input is selected by register control, or by defining a universal hardware input pin as CLKIN_SEL in ClockBuilder Pro.

A register bit determines input selection as pin or register selectable. If a universal input pin is defined as CLKIN_SEL, that pin is selec-

ted by default and is internally pulled high so that the free-run mode is automatically selected when left unconnected. If there is no clock

signal on the selected input, the device will not generate output clocks.

In a typical application, the Si5332 reference input is configured immediately after power-up and initialization. If the device is switched

to another input more than ±1000 ppm offset from the initial input, the device must be recalibrated manually to the new frequency, tem-

porarily turning off the clock outputs. After the VCO is recalibrated, the device will resume producing clock outputs. If the selected inputs

are within ±1000 ppm, any phase error difference will propagate through the device at a rate determined by the PLL bandwidth. Hitless

switching and phase build-out are not supported by the Si5332.

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