KSZ9031RNXIA Просмотр технического описания (PDF) - Micrel

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KSZ9031RNXIA

Gigabit Ethernet Transceiver with RGMII Support

Micrel 

Micrel, Inc.

KSZ9031RNX

Table 4 details the four registers located at MMD Address 2h that are provided for pad skew programming.

Table 4. RGMII Pad Skew Registers

Address Name

Description

Mode

Default

MMD Address 2h, Register 4h – RGMII Control Signal Pad Skew

2.4.15:8

Reserved

Reserved

RW

2.4.7:4

RX_DV

Pad Skew

RGMII RX_CTL output pad skew control (0.06ns/step)

RW

2.4.3:0

TX_EN

Pad Skew

RGMII TX_CTL input pad skew control (0.06ns/step)

RW

0000_0000

0111

0111

MMD Address 2h, Register 5h – RGMII RX Data Pad Skew

2.5.15:12

RXD3

Pad Skew

RGMII RXD3 output pad skew control (0.06ns/step)

2.5.11:8

RXD2

Pad Skew

RGMII RXD2 output pad skew control (0.06ns/step)

2.5.7:4

RXD1

Pad Skew

RGMII RXD1 output pad skew control (0.06ns/step)

2.5.3:0

RXD0

Pad Skew

RGMII RXD0 output pad skew control (0.06ns/step)

RW

0111

RW

0111

RW

0111

RW

0111

MMD Address 2h, Register 6h – RGMII TX Data Pad Skew

2.6.15:12

TXD3

Pad Skew

RGMII TXD3 input pad skew control (0.06ns/step)

2.6.11:8

TXD2

Pad Skew

RGMII TXD2 input pad skew control (0.06ns/step)

2.6.7:4

TXD1

Pad Skew

RGMII TXD1 input pad skew control (0.06ns/step)

2.6.3:0

TXD0

Pad Skew

RGMII TXD0 input pad skew control (0.06ns/step)

RW

0111

RW

0111

RW

0111

RW

0111

MMD Address 2h, Register 8h – RGMII Clock Pad Skew

2.8.15:10 Reserved

Reserved

RW

2.8.9:5

GTX_CLK

Pad Skew

RGMII GTX_CLK input pad skew control (0.06ns/step)

RW

2.8.4:0

RX_CLK

Pad Skew

RGMII RX_CLK output pad skew control (0.06ns/step)

RW

0000_00

01_111

0_1111

May 14, 2015

24

Revision 2.2

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