KSZ9031RNX Просмотр технического описания (PDF) - Micrel

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KSZ9031RNX

Gigabit Ethernet Transceiver with RGMII Support

Micrel 

Micrel, Inc.

KSZ9031RNX

Analog-to-Digital Converter (ADC)

In 1000Base-T mode, the analog-to-digital converter (ADC) digitizes the incoming signal. ADC performance is essential to

the overall performance of the transceiver.

This circuit is disabled in 10Base-T/100Base-TX mode.

Timing Recovery Circuit

In 1000Base-T mode, the mixed-signal clock recovery circuit together with the digital phase-locked loop is used to recover

and track the incoming timing information from the received data. The digital phase-locked loop has very low long-term

jitter to maximize the signal-to-noise ratio of the receive signal.

The 1000Base-T slave PHY must transmit the exact receive clock frequency recovered from the received data back to the

1000Base-T master PHY. Otherwise, the master and slave will not be synchronized after long transmission. This also

helps to facilitate echo cancellation and NEXT removal.

Adaptive Equalizer

In 1000Base-T mode, the adaptive equalizer provides the following functions:

• Detection for partial response signaling

• Removal of NEXT and ECHO noise

• Channel equalization

Signal quality is degraded by residual echo that is not removed by the analog hybrid because of impedance mismatch.

The KSZ9031RNX uses a digital echo canceller to further reduce echo components on the receive signal.

In 1000Base-T mode, data transmission and reception occurs simultaneously on all four pairs of wires (four channels).

This results in high-frequency cross-talk coming from adjacent wires. The KSZ9031RNX uses three NEXT cancellers on

each receive channel to minimize the cross-talk induced by the other three channels.

In 10Base-T/100Base-TX mode, the adaptive equalizer needs only to remove the inter-symbol interference and recover

the channel loss from the incoming data.

Trellis Encoder and Decoder

In 1000Base-T mode, the transmitted 8-bit data is scrambled into 9-bit symbols and further encoded into 4D-PAM5

symbols. The initial scrambler seed is determined by the specific PHY address to reduce EMI when more than one

KSZ9031RNX is used on the same board. On the receiving side, the idle stream is examined first. The scrambler seed,

pair skew, pair order, and polarity must be resolved through the logic. The incoming 4D-PAM5 data is then converted into

9-bit symbols and de-scrambled into 8-bit data.

May 14, 2015

18

Revision 2.2

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