KSZ9031RNX(2012) Просмотр технического описания (PDF) - Micrel

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Компоненты Описание

производитель

KSZ9031RNX
(Rev.:2012)

Gigabit Ethernet Transceiver with RGMII Support

Micrel 

Micrel, Inc.

KSZ9031RNX

Auto-Negotiation Interval Timers

Transmit burst interval

Transmit pulse interval

FLP detect minimum time

FLP detect maximum time

Receive minimum burst interval

Receive maximum burst interval

Data detect minimum interval

Data detect maximum interval

NLP test minimum interval

NLP test maximum interval

Link loss time

Break link time

Parallel detection wait time

Link enable wait time

Time Duration

16 ms

68 µs

17.2 µs

185 µs

6.8 ms

112 ms

35.4 µs

95 µs

4.5 ms

30 ms

52 ms

1480 ms

830 ms

1000 ms

Table 2. Auto-Negotiation Timers

RGMII Interface

The Reduced Gigabit Media Independent Interface (RGMII) supports on-chip data-to-clock delay timing according to the

RGMII Version 2.0 Specification, with programming options for external delay timing and to adjust and correct TX and RX

timing paths.

RGMII provides a common interface between RGMII PHYs and MACs, and has the following key characteristics:

• Pin count is reduced from 24 pins for the IEEE Gigabit Media Independent Interface (GMII) to 12 pins for RGMII.

• All speeds (10Mbps, 100Mbps, and 1000Mbps) are supported at both half- and full-duplex.

• Data transmission and reception are independent and belong to separate signal groups.

• Transmit data and receive data are each four bits wide, a nibble.

In RGMII operation, the RGMII pins function as follows:

• The MAC sources the transmit reference clock, TXC, at 125MHz for 1000Mbps, 25MHz for 100Mbps, and

2.5MHz for 10Mbps.

• The PHY recovers and sources the receive reference clock, RXC, at 125MHz for 1000Mbps, 25MHz for

100Mbps, and 2.5MHz for 10Mbps..

• For 1000Base-T, the transmit data, TXD[3:0], is presented on both edges of TXC, and the received data,

RXD[3:0], is clocked out on both edges of the recovered 125MHz clock, RXC.

• For 10Base-T/100Base-TX, the MAC holds TX_CTL low until both PHY and MAC operate at the same speed.

During the speed transition, the receive clock is stretched on either a positive or negative pulse to ensure that

no clock glitch is presented to the MAC.

• TX_ER and RX_ER are combined with TX_EN and RX_DV, respectively, to form TX_CTL and RX_CTL. These

two RGMII control signals are valid at the falling clock edge.

After power-up or reset, the KSZ9031RNX is configured to RGMII mode if the MODE[3:0] strap-in pins are set to one of

the RGMII mode capability options. See the “Strapping Options” section for available options.

The KSZ9031RNX has the option to output a 125MHz reference clock on the CLK125_NDO pin. This clock provides a

lower-cost reference clock alternative for RGMII MACs that require a 125MHz crystal or oscillator. The 125MHz clock

output is enabled after power-up or reset if the CLK125_EN strap-in pin is pulled high.

October 2012

22

M9999-103112-1.0

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