KSZ9031RNX(2012) Просмотр технического описания (PDF) - Micrel

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Компоненты Описание

производитель

KSZ9031RNX
(Rev.:2012)

Gigabit Ethernet Transceiver with RGMII Support

Micrel 

Micrel, Inc.

KSZ9031RNX

Pin Number

31

32

33

34

35

36

Pin Name

RXD1/

MODE1

RXD0/

MODE0

RX_DV/

CLK125_EN

DVDDH

RX_CLK/

PHYAD2

MDC

37

MDIO

38

INT_N/

PME_N2

39

DVDDL

40

DVDDH

41

CLK125_NDO/

LED_MODE

42

RESET_N

43

LDO_O

44

AVDDL_PLL

45

XO

46

XI

47

NC

Type(1)

I/O

I/O

I/O

P

I/O

Ipu

Ipu/O

O

P

P

I/O

Ipu

O

P

O

I

–

Pin Function

RGMII mode: RGMII RD1 (Receive Data 1) output

Config mode: The pull-up/pull-down value is latched as MODE1 during

power-up/reset. See the “Strapping Options” section for details.

RGMII mode: RGMII RD0 (Receive Data 0) output

Config mode:

The pull-up/pull-down value is latched as MODE0 during

power-up/reset. See the “Strapping Options” section for details.

RGMII mode: RGMII RX_CTL (Receive Control) output

Config mode: Latched as CLK125_NDO Output Enable during

power-up/reset. See the “Strapping Options” section for details.

3.3V, 2.5V, or 1.8V digital VDD_I/O

RGMII mode: RGMII RXC (Receive Reference Clock) output

Config mode: The pull-up/pull-down value is latched as PHYAD[2] during

power-up/reset. See the “Strapping Options” section for details.

Management data clock input

This pin is the input reference clock for MDIO (pin 37).

Management data input/output

This pin is synchronous to MDC (pin 36) and requires an external pull-up resistor

to DVDDH (digital VDD_I/O) in a range from 1.0kΩ to 4.7kΩ.

Interrupt output: Programmable interrupt output, with register 1Bh as the Interrupt

Control/Status register, for programming the interrupt conditions

and reading the interrupt status. Register 1Fh, bit [14] sets

the interrupt output to active low (default) or active high.

PME_N output: Programmable PME_N output (pin option 2). When asserted

low, this pin signals that a WOL event has occurred.

For Interrupt (when active low) and PME functions, this pin requires an external

pull-up resistor to DVDDH (digital VDD_I/O) in a range from 1.0kΩ to 4.7kΩ.

1.2V digital VDD

3.3V, 2.5V, or 1.8V digital VDD_I/O

125MHz clock output

This pin provides a 125MHz reference clock output option for use by the MAC.

Config mode: The pull-up/pull-down value is latched as LED_MODE during

power-up/reset. See the “Strapping Options” section for details.

Chip reset (active low)

Hardware pin configurations are strapped-in at the de-assertion (rising edge) of

RESET_N. See the “Strapping Options” section for more details.

On-chip 1.2V LDO controller output

This pin drives the input gate of a P-channel MOSFET to generate 1.2V for the

chip’s core voltages. If the system provides 1.2V and this pin is not used, it can be

left floating.

1.2V analog VDD for PLL

25MHz crystal feedback

This pin is a no connect if an oscillator or external clock source is used.

Crystal / Oscillator/ External Clock input

25MHz ±50ppm tolerance

No connect

This pin is not bonded and can be connected to AVDDH power for footprint

compatibility with the Micrel KSZ9021RN Gigabit PHY.

October 2012

13

M9999-103112-1.0

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