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ST7263BE1 Просмотр технического описания (PDF) - STMicroelectronics

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ST7263BE1 Datasheet PDF : 186 Pages
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Introduction
Figure 1. General block diagram
OSCIN
OSCOUT
VDD
VSS
RESET
OSCILLATOR
INTERNAL
CLOCK
OSC/3
OSC/4 or OSC/2
for USB2)
POWER
SUPPLY
WATCHDOG
CONTROL
8-BIT CORE
ALU
LVD
USB DMA
VPP/TEST
VDDA
VSSA
PROGRAM
MEMORY
(32K Bytes)
RAM
(1024 Bytes)
ST7263Bxx
I²C
PORT A
16-BIT TIMER
PORT B
ADC(1)
PORT D
PORT C
SCI
(UART)
USB SIE
PA[7:0]
(8 bits)
PB[7:0]
(8 bits)
PD[7:0]
(8 bits)
PC[2:0]
(3 bits)
USBDP
USBDM
USBVCC
1. ADC channels:
12 on 48-pin devices (Port B and Port D[3:0])
8 on 34 and 32-pin devices (Port B)
None on 24-pin devices
2. 12 or 24 MHz OSCIN frequency required to generate 6 MHz USB clock.
3. The drive from USBVCC is sufficient to only drive an external pull-up in addition to the internal transceiver.
12/186
Doc ID 7516 Rev 8

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