EM78P156 Просмотр технического описания (PDF) - Elan Microelectronics Corp

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Компоненты Описание

производитель

EM78P156

8-BIT MICRO-CONTROLLER

Elan Microelectronics Corp 

EM78P156E

Table 10 The list of the instruction set of EM78P156E

INSTRUCTION

BINARY

0 0000 0000 0000

0 0000 0000 0001

0 0000 0000 0010

0 0000 0000 0011

0 0000 0000 0100

0 0000 0000 rrrr

0 0000 0001 0000

0 0000 0001 0001

0 0000 0001 0010

0 0000 0001 0011

0 0000 0001 0100

0 0000 0001 rrrr

0 0000 01rr rrrr

0 0000 1000 0000

0 0000 11rr rrrr

0 0001 00rr rrrr

0 0001 01rr rrrr

0 0001 10rr rrrr

0 0001 11rr rrrr

0 0010 00rr rrrr

0 0010 01rr rrrr

0 0010 10rr rrrr

0 0010 11rr rrrr

0 0011 00rr rrrr

0 0011 01rr rrrr

0 0011 10rr rrrr

0 0011 11rr rrrr

0 0100 00rr rrrr

0 0100 01rr rrrr

0 0100 10rr rrrr

0 0100 11rr rrrr

0 0101 00rr rrrr

0 0101 01rr rrrr

0 0101 10rr rrrr

0 0101 11rr rrrr

0 0110 00rr rrrr

0 0110 01rr rrrr

0 0110 10rr rrrr

0 0110 11rr rrrr

0 0111 00rr rrrr

0 0111 01rr rrrr

0 0111 10rr rrrr

0 0111 11rr rrrr

HEX

MNEMONIC

OPERATION

0000

NOP

No Operation

0001

0002

0003

0004

000r

DAA

CONTW

SLEP

WDTC

IOW R

Decimal Adjust A

A → CONT

0 → WDT, Stop oscillator

0 → WDT

A → IOCR

0010

ENI

Enable Interrupt

0011

0012

0013

DISI

RET

RETI

Disable Interrupt

[Top of Stack] → PC

[Top of Stack] → PC,

Enable Interrupt

0014

001r

00rr

0080

00rr

01rr

01rr

01rr

01rr

02rr

02rr

02rr

02rr

03rr

03rr

03rr

03rr

04rr

04rr

04rr

04rr

05rr

05rr

05rr

05rr

06rr

06rr

06rr

06rr

07rr

07rr

07rr

CONTR

IOR R

MOV R,A

CLRA

CLR R

SUB A,

SUB R,A

DECA R

DEC R

OR A,R

OR R,A

AND A,R

AND R,A

XOR A,R

XOR R,A

ADD A,R

ADD R,A

MOV A,R

MOV R,R

COMA R

COM R

INCA R

INC R

DJZA

DJZ R

RRCA R

RRC R

RLCA R

RLC R

SWAPA R

SWAP R

JZA R

CONT → A

IOCR → A

A→R

0→A

0→R

R R-A → A

R-A → R

R-1 → A

R-1 → R

A ∨ VR → A

A ∨ VR → R

A&R→A

A&R→R

A⊕R→A

A⊕R→R

A+R→A

A+R→R

R→A

R→R

/R → A

/R → R

R+1 → A

R+1 → R

R R-1 → A, skip if zero

R-1 → R, skip if zero

R(n) → A(n-1)

R(0) → C, C → A(7)

R(n) → R(n-1)

R(0) → C, C → R(7)

R(n) → A(n+1)

R(7) → C, C → A(0)

R(n) → R(n+1)

R(7) → C, C → R(0)

R(0-3) → A(4-7)

R(4-7) → A(0-3)

R(0-3) ↔ R(4-7)

R+1 → A, skip if zero

07rr

JZ R

R+1 → R, skip if zero

* This specification is subject to be changed without notice. 8.11.1999

B3-24

STATUS

AFFECTED

None

C

None

T,P

T,P

None <Note1>

None

None

None

None

None

None <Note1>

None

Z

Z

Z,C,DC

Z,C,DC

Z

Z

Z

Z

Z

Z

Z

Z

Z,C,DC

Z,C,DC

Z

Z

Z

Z

Z

Z

None

None

C

C

C

C

None

None

None

None

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