TEA5767HN Просмотр технического описания (PDF) - Philips Electronics

Номер в каталоге

Компоненты Описание

производитель

TEA5767HN

Low-power FM stereo radio for handheld applications

Philips Electronics 

Philips Semiconductors

TEA5767HN

Low-power FM stereo radio for handheld applications

SDA

tf

SCL

tLOW

tr

tHD;STA

tSU;DAT

tf

tBUF

tHD;STA

tSU;BUSEN

tHD;DAT

tSU;STA

tHIGH

tSU;STO

tHO;BUSEN

BUSENABLE

001aae349

Fig 6.

tf = fall time of both SDA and SCL signals: 20 + 0.1Cb < tf < 300 ns, where Cb = capacitive load on bus line in pF.

tr = rise time of both SDA and SCL signals: 20 + 0.1Cb < tf < 300 ns, where Cb = capacitive load on bus line in pF.

tHD;STA = hold time (repeated) START condition. After this period, the first clock pulse is generated: > 600 ns.

tHIGH = HIGH period of the SCL clock: > 600 ns.

tSU;STA = set-up time for a repeated START condition: > 600 ns.

tHD;DAT = data hold time: 300 ns < tHD;DAT < 900 ns.

Remark: 300 ns lower limit is added because the ASIC has no internal hold time for the SDA signal.

tSU;DAT = data set-up time: tSU;DAT > 100 ns. If ASIC is used in a standard mode I2C-bus system, tSU;DAT > 250 ns.

tSU;STO = set-up time for STOP condition: > 600 ns.

tBUF = bus free time between a STOP and a START condition: > 600 ns.

Cb = capacitive load of one bus line: < 400 pF.

tSU;BUSEN = bus enable set-up time: tSU;BUSEN > 10 µs.

tHO;BUSEN = bus enable hold time: tHO;BUSEN > 10 µs.

I2C-bus timing diagram

8.3 3-wire bus specification

The 3-wire bus controls the write/read, clock and data lines and operates at a maximum

clock frequency of 400 kHz.

Hint: By using the standby bit the IC can be switched into a low current Standby mode. In

Standby mode the IC must be in the WRITE mode. When the IC is switched to READ

mode, during standby, the IC will hold the data line down. The standby current can be

reduced by deactivating the bus interface (pin BUSENABLE LOW). If the bus interface is

deactivated (pin BUSENABLE LOW) without the Standby mode being programmed, the

IC maintains normal operation, but is isolated from the clock and data line.

8.3.1 Data transfer

Data sequence: byte 1, byte 2, byte 3, byte 4 and byte 5 (the data transfer has to be in this

order).

A positive edge at pin WRITE/READ enables the data transfer into the IC. The data has to

be stable at the positive edge of the clock. Data may change while the clock is LOW and is

written into the IC on the positive edge of the clock. Data transfer can be stopped after the

transmission of new tuning information with the first two bytes or after each following byte.

TEA5767HN_4

Product data sheet

Rev. 04 — 20 February 2006

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

12 of 39

Share Link: