MFRC522_(2007) Просмотр технического описания (PDF) - NXP Semiconductors.
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MFRC522_ Datasheet PDF : 109 Pages
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NXP Semiconductors
MFRC522
Contactless Reader IC
9.2.1.4 DivIEnReg
Control bits to enable and disable the passing of interrupt requests.
Table 13: DivIEnReg register (address 03h); reset value: 00h
Bit
7
6
5
4
3
Symbol IRQPushPull
-
MfinActIEn
-
Access
r/w
Rights
RFU
r/w
RFU
2
CRCIEn
r/w
1
0
-
RFU
Table 14: Description of DivIEnReg bits
Bit
Symbol
Description
7
IRQPushPull Set to logic 1, the pin IRQ works as standard CMOS output pad.
Set to logic 0, the pin IRQ works as open drain output pad.
6 to 5 -
Reserved for future use.
4
MfinActIEn Allows the MFIN active interrupt request to be propagated to pin IRQ.
3
-
Reserved for future use.
2
CRCIEn
Allows the CRC interrupt request (indicated by bit CRCIRq) to be
propagated to pin IRQ.
1 to 0 -
Reserved for future use.
9.2.1.5 CommIRqReg
Contains Interrupt Request bits.
Table 15:
Bit
Symbol
Access
Rights
CommIRqReg register (address 04h); reset value: 14h
7
6
5
4
3
2
Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq
w
dy
dy
dy
dy
dy
1
ErrIRq
dy
0
TimerIRq
dy
112132
Product data sheet
Table 16: Description of CommIRqReg bits
All bits in the register CommIRqReg shall be cleared by software.
Bit Symbol Description
7 Set1
Set to logic 1, Set1 defines that the marked bits in the register CommIRqReg
are set.
Set to logic 0, Set1 defines, that the marked bits in the register CommIRqReg
are cleared.
6 TxIRq
Set to logic 1 immediately after the last bit of the transmitted data was sent out.
5 RxIRq
Set to logic 1 when the receiver detects the end of a valid data stream.
If the bit RxNoErr in register RxModeReg is set to logic 1, Bit RxIRq is only set
to logic 1 when data bytes are available in the FIFO.
4 IdleIRq
Set to logic 1, when a command terminates by itself e.g. when the
CommandReg changes its value from any command to the Idle Command.
If an unknown command is started, the CommandReg changes its content to
the idle state and the bit IdleIRq is set. Starting the Idle Command by the
μ-Controller does not set bit IdleIRq.
3 HiAlertIRq Set to logic 1, when bit HiAlert in register Status1Reg is set. In opposition to
HiAlert, HiAlertIRq stores this event and can only be reset as indicated by bit
Set1.
Rev. 3.2 — 22 May 2007
© NXP B.V. 2007. All rights reserved.
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