MFRC522_(2007) Просмотр технического описания (PDF) - NXP Semiconductors.
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MFRC522_ Datasheet PDF : 109 Pages
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NXP Semiconductors
MFRC522
Contactless Reader IC
Table 64: Description of MifNFCReg bits . . . . . . . . . 31
Table 65: MfRxReg register (address 1Dh); reset
value: 00h. . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 66: Description of ManualRCVReg bits . . . . . 32
Table 67: Reserved register (address 1Eh); reset
value: 00h. . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 68: Description of Reserved register bits . . . . 32
Table 69: SerialSpeedReg register (address 1Fh);
reset value: EBh . . . . . . . . . . . . . . . . . . . . 32
Table 70: Description of SerialSpeedReg bits . . . . . 32
Table 71: Reserved register (address 20h); reset
value: 00h. . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 72: Description of Reserved register bits . . . . 33
Table 73: CRCResultReg register (address 21h); reset
value: FFh . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 74: Description of CRCResultReg higher bits 33
Table 75: CRCResultReg register (address 22h); reset
value: FFh . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 76: Description of CRCResultReg lower bits . 33
Table 77: Reserved register (address 23h); reset
value: 88h. . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 78: Description of Reserved register bits . . . . 34
Table 79: ModWidthReg register (address 24h); reset
value: 26h. . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 80: Description of ModWidthReg bits . . . . . . . 34
Table 81: Reserved register (address 25h); reset
value: 87h. . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 82: Description of Reserved register bits . . . . 34
Table 83: RFCfgReg register (address 26h); reset
value: 48h. . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 84: Description of RFCfgReg bits . . . . . . . . . . 35
Table 85: GsNReg register (address 27h); reset value:
88h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 86: Description of GsNOnReg bits . . . . . . . . . 35
Table 87: CWGsPReg register (address 28h); reset
value: 20h. . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 88: Description of CWGsPReg bits . . . . . . . . 36
Table 89: ModGsPReg register (address 29h); reset
value: 20h. . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 90: Description of ModGsPReg bits . . . . . . . . 36
Table 91: TModeReg register (address 2Ah); reset
value: 00h. . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 92: Description of TModeReg bits . . . . . . . . . 37
Table 93: TPrescalerReg register (address 2Bh); reset
value: 00h. . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 94: Description of TPrescalerReg bits . . . . . . 37
Table 95: TReloadReg (Higher bits) register (address
2Ch); reset value: 00h . . . . . . . . . . . . . . . 38
Table 96: Description of higher TReloadReg bits. . . 38
Table 97: TReloadReg (Lower bits)register (address
2Dh); reset value: 00h . . . . . . . . . . . . . . . 38
Table 98: Description of lower TReloadReg bits . . . 38
Table 99: TCounterValReg (Higher bits) register
(address 2Eh); reset value: XXh . . . . . . . 39
Table 100:Description of higher TCounterValReg bits.
39
Table 101:TCounterValReg (Lower bits) register
(address 2Fh); reset value: XXh . . . . . . . 39
Table 102:Description of lower TCounterValReg bits .
39
Table 103:Reserved register (address 30h); reset
value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 104:Description of Reserved register bits . . . 39
Table 105:TestSel1Reg register (address 31h); reset
value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 106:Description of TestSel1Reg bits . . . . . . . 40
Table 107: TestSel2Reg register (address 32h); reset
value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 108:Description of TestSel2Reg bits . . . . . . . 40
Table 109:TestPinEnReg register (address 33h); reset
value: 80h . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 110:Description of TestPinEnReg bits . . . . . . 41
Table 111: TestPinValueReg register (address 34h);
reset value: 00h . . . . . . . . . . . . . . . . . . . . 41
Table 112:Description of TestPinValueReg bits . . . . 41
Table 113: TestBusReg register (address 35h); reset
value: XXh . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 114:Description of TestBusReg bits . . . . . . . . 42
Table 115: AutoTestReg register (address 36h); reset
value: 40h . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 116:Description of AutoTestReg bits . . . . . . . 42
Table 117: VersionReg register (address 37h); reset
value: XXh . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 118:Description of VersionReg bits . . . . . . . . 42
Table 119: AnalogTestReg register (address 38h);
reset value: 00h . . . . . . . . . . . . . . . . . . . . 43
Table 120:Description of AnalogTestReg bits . . . . . 43
Table 121: TestDAC1Reg register (address 39h); reset
value: XXh . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 122:Description of TestDAC1Reg bits . . . . . . 44
Table 123:TestDAC2Reg register (address 3Ah); reset
value: XXh . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 124:Description ofTestDAC2Reg bits . . . . . . 44
Table 125: TestADCReg register (address 3Bh); reset
value: XXh . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 126:Description of TestADCReg bits . . . . . . . 44
Table 127: Reserved register (address 3Ch); reset
value: FFh . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 128:Description of Reserved register bits . . . 45
Table 129:Reserved register (address 3Dh); reset
value: 00h . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 130:Description of Reserved register bits . . . 45
continued >>
112132
Product data sheet
Rev. 3.2 — 22 May 2007
© NXP B.V. 2007. All rights reserved.
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