AM28F512 Просмотр технического описания (PDF) - Advanced Micro Devices
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AM28F512 Datasheet PDF : 35 Pages
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Section
Addresses
A
B
C
D
E
F
G
CE#
OE#
WE#
Data
VCC
20h
20h
A0h
Data
Out
VPP
Bus Cycle
Command
Function
A
Write
20h
Erase
Setup
B
Write
20h
Erase
C
Time-out
N/A
Erase
(10 ms)
D
Write
A0h
Erase-
Verify
E
Time-out
N/A
Transition
(6 µs)
11559G-7
F
Read
Compare
Data
Erase
Verification
G
Standby
N/A
Proceed per
Erase
Algorithm
Figure 2. AC Waveforms For Erase Operations
ANALYSIS OF ERASE TIMING WAVEFORM
Note: This analysis does not include the requirement
to program the entire array to 00h data prior to erasure.
Refer to the Flashrite Programming algorithm.
Erase Setup/Erase
This analysis illustrates the use of two-cycle erase
commands (section A and B). The first erase com-
mand (20h) is a Setup command and does not affect
the array data (section A). The second erase com-
mand (20h) initiates the erase operation (section B)
on the rising edge of this WE# pulse. All bytes of the
memory array are erased in parallel. No address infor-
mation is required.
The erase pulse occurs in section C.
Time-Out
A software timing routine (10 ms duration) must be ini-
tiated on the rising edge of the WE# pulse of section B.
Note: An integrated stop timer prevents any possibil-
ity of overerasure by limiting each time-out period of
10 ms.
Erase-Verify
Upon completion of the erase software timing routine,
the microprocessor must write the Erase-verify com-
mand (A0h). This command terminates the erase oper-
ation on the rising edge of the WE# pulse (section D).
The Erase-verify command also stages the device for
data verification (section F).
After each erase operation each byte must be verified.
The byte address to be verified must be supplied with
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Am28F512
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