STM32F301C6(2014) Просмотр технического описания (PDF) - STMicroelectronics
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производитель
STM32F301C6
(Rev.:2014)
(Rev.:2014)
STMicroelectronics
STM32F301C6 Datasheet PDF : 132 Pages
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STM32F301x6 STM32F301x8
Functional overview
3.4
Cyclic redundancy check calculation unit (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at
linktime and stored at a given memory location.
3.5
3.5.1
Power management
Power supply schemes
VSS, VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. It is
provided externally through VDD pins.
VSSA, VDDA = 2.0 to 3.6 V: external analog power supply for ADC, DAC, comparators,
operational amplifier, reset blocks, RCs and PLL. The minimum voltage to be applied to
VDDA differs from one analog peripheral to another. Table 3 provides the summary of
the VDDA ranges for analog peripherals. The VDDA voltage level must always be greater
than or equal to the VDD voltage level and must be provided first.
Table 3. External analog supply values for analog peripherals
Analog peripheral
Minimum VDDA supply
Maximum VDDA supply
ADC/COMP
2.0 V
3.6 V
DAC/OPAMP
2.4 V
3.6 V
3.5.2
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Power supply supervisor
The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 2 V. The device
remains in reset mode when the monitored supply voltage is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit.
The POR monitors only the VDD supply voltage. During the startup phase it is required
that VDDA should arrive first and be greater than or equal to VDD.
The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce
the power consumption if the application design ensures that VDDA is higher than or
equal to VDD.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD power supply and compares it to the VPVD threshold. An interrupt can be generated
when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD
threshold. The interrupt service routine can then generate a warning message and/or put
the MCU into a safe state. The PVD is enabled by software.
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