PSD4246G6V-20UI Просмотр технического описания (PDF) - STMicroelectronics

Номер в каталоге

Компоненты Описание

производитель

PSD4246G6V-20UI

Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

STMicroelectronics 

PSD4235G2

Primary Flash Memory and Secondary Flash

memory Description. The primary Flash memo-

ry is divided evenly into 8 sectors. The secondary

Flash memory is divided evenly into 4 sectors.

Each sector of either memory block can be sepa-

rately protected from Program and Erase cycles.

Flash memory may be erased on a sector-by-sec-

tor basis, and programmed word-by-word. Flash

sector erasure may be suspended while data is

read from other sectors of the block and then re-

sumed after reading.

During a Program or Erase cycle in Flash memory,

the status can be output on the Ready/Busy pin

(PE4). This pin is set up using PSDsoft Express.

Memory Block Select Signals. The DPLD gen-

erates the Select signals for all the internal memo-

ry blocks (see the section entitled “PLDs”, on page

31). Each of the sectors of the primary Flash mem-

ory has a Select signal (FS0-FS7) which can con-

tain up to three product terms. Each of the sectors

of the secondary Flash memory has a Select sig-

nal (CSBOOT0-CSBOOT3) which can contain up

to three product terms. Having three product terms

for each Select signal allows a given sector to be

mapped in different areas of system memory.

When using a MCU with separate Program and

Data space (80C51XA), these flexible Select sig-

nals allow dynamic re-mapping of sectors from

one memory space to the other before and after

IAP. The SRAM block has a single Select signal

(RS0).

Ready/Busy (PE4). This signal can be used to

output the Ready/Busy status of the PSD. The out-

put is a 0 (Busy) when a Flash memory block is be-

ing written to, or when a Flash memory block is

being erased. The output is a 1 (Ready) when no

Write or Erase cycle is in progress.

Memory Operation. The primary Flash memory

and secondary Flash memory are addressed

through the MCU Bus Interface. The MCU can ac-

cess these memories in one of two ways:

s The MCU can execute a typical bus Write or

Read operation just as it would if accessing a

RAM or ROM device using standard bus cycles.

s The MCU can execute a specific instruction that

consists of several Write and Read operations.

This involves writing specific data patterns to

special addresses within the Flash memory to

invoke an embedded algorithm. These

instructions are summarized in Table 29.

Typically, the MCU can read Flash memory using

Read operations, just as it would read a ROM de-

vice. However, Flash memory can only be erased

and programmed using specific instructions. For

example, the MCU cannot write a single byte di-

rectly to Flash memory as one would write a byte

to RAM. To program a word into Flash memory,

the MCU must execute a Program instruction, then

test the status of the Programming event. This sta-

tus test is achieved by a Read operation or polling

Ready/Busy (PE4).

Flash memory can also be read by using special

instructions to retrieve particular Flash device in-

formation (sector protect status and ID).

21/89

Share Link: