PSD4246G3V-90U Просмотр технического описания (PDF) - STMicroelectronics

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PSD4246G3V-90U

Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

STMicroelectronics 

PSD4235G2

Table 20. Flash Boot Protection Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Security_Bit not used

not used

not used

Sec3_Prot

Note: Bit Definitions:

Sec<i>_Prot 1 = Secondary Flash memory Sector <i> is write protected.

Sec<i>_Prot 0 = Secondary Flash memory Sector <i> is not write protected.

Security_Bit 0 = Security Bit in device has not been set.

Security_Bit 1 = Security Bit in device has been set.

Bit 2

Sec2_Prot

Bit 1

Sec1_Prot

Bit 0

Sec0_Prot

Table 21. JTAG Enable Register

Bit 7

Bit 6

Bit 5

not used

not used

not used

Note: Bit Definitions:

JTAGEnable 1 = JTAG Port is enabled.

JTAGEnable 0 = JTAG Port is disabled.

Bit 4

not used

Bit 3

not used

Bit 2

not used

Bit 1

not used

Bit 0

JTAGEnable

Table 22. Page Register

Bit 7

Bit 6

Bit 5

Bit 4

PGR 7

PGR 6

PGR 5

PGR 4

Note: Bit Definitions:

Configure Page input to PLD. Default is PGR7-PGR0=0.

Bit 3

PGR 3

Bit 2

PGR 2

Bit 1

PGR 1

Bit 0

PGR 0

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