PSD4246F1-20U Просмотр технического описания (PDF) - STMicroelectronics

Номер в каталоге

Компоненты Описание

производитель

PSD4246F1-20U

Flash In-System Programmable (ISP) Peripherals For 16-bit MCUs (5V Supply)

STMicroelectronics 

PSD4235G2

PSD REGISTER DESCRIPTION AND ADDRESS OFFSETS

Table 6 shows the offset addresses to the PSD

registers relative to the CSIOP base address. The

CSIOP space is the 256 bytes of address that is al-

located by the user to the internal PSD registers.

Table 6 provides brief descriptions of the registers

in CSIOP space. The following sections give a

more detailed description.

Table 6. Register Address Offset

Register Name

Port

A

Port Port Port

BCD

Port

E

Port Port

FG

Other1

Description

Data In

00 01 10 11 30 40 41

Reads Port pin as input, MCU I/O input mode

Control

32 42 43

Selects mode between MCU I/O or Address

Out

Data Out

04 05 14 15 34 44 45

Stores data for output to Port pins, MCU I/O

output mode

Direction

06 07 16 17 36 46 47

Configures Port pin as input or output

Drive Select

08 09 18 19 38 48 49

Configures Port pins as either CMOS or

Open Drain on some pins, while selecting

high slew rate on other pins.

Input Macrocell 0A 0B

1A

Reads Input Macrocells

Enable Out

0C 0D 1C

4C

Reads the status of the output enable to the

I/O Port driver

Output

Macrocells A

20

Read – reads output of Macrocells A

Write – loads Macrocell Flip-flops

Output

Macrocells B

21

Read – reads output of Macrocells B

Write – loads Macrocell Flip-flops

Mask

Macrocells A

22

Blocks writing to the Output Macrocells A

Mask

Macrocells B

23

Blocks writing to the Output Macrocells B

Flash Memory

Protection

C0 Read only – Primary Flash Sector Protection

Flash Boot

Protection

C2

Read only – PSD Security and Secondary

Flash memory Sector Protection

JTAG Enable

C7 Enables JTAG Port

PMMR0

B0 Power Management Register 0

PMMR2

B4 Power Management Register 2

Page

E0 Page Register

VM

E2

Places PSD memory areas in Program and/

or Data space on an individual basis.

Memory_ID0

F0

Read only – SRAM and Primary memory

size

Memory_ID1

F1

Read only – Secondary memory type and

size

Note: 1. Other registers that are not part of the I/O ports.

14/89

Share Link: