DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

PSD4246G2V-90U Просмотр технического описания (PDF) - STMicroelectronics

Номер в каталоге
Компоненты Описание
производитель
PSD4246G2V-90U Datasheet PDF : 89 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
PSD4235G2
Pin Name Pin Type
Description
PE3
74
I/O
CMOS
or
Open
Drain
PE3 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TDO output for the JTAG Serial Interface.
I/O
PE4 pin of Port E. This port pin can be configured to have the following functions:
CMOS 1. MCU I/O – standard output or input port.
PE4
75
or
2. Latched address output.
Open 3. TSTAT output for the JTAG Serial Interface.
Drain 4. Ready/Busy output for parallel In-System Programming (ISP).
PE5
76
I/O
CMOS
or
Open
Drain
PE5 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TERR active Low output for the JTAG Serial Interface.
PE6
77
I/O
CMOS
or
Open
Drain
PE6 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. VSTBY – SRAM stand-by voltage input for SRAM battery backup.
I/O
PE7 pin of Port E. This port pin can be configured to have the following functions:
CMOS 1. MCU I/O – standard output or input port.
PE7
78
or
2. Latched address output.
Open 3. Battery-on Indicator (VBATON). Goes High when power is being drawn from the
Drain external battery.
PF0-PF7
31-38
I/O
CMOS
or
Open
Drain
These pins make up Port F. These port pins are configurable and can have the following
functions:
1. MCU I/O – standard output or input port.
2. External Chip Select (ECS0-ECS7) outputs, or inputs to CPLD.
3. Latched address outputs.
4. Address A1-A3 inputs in 80C51XA mode (PF0 is grounded)
5. Data bus port (D0-D7) in a non-multiplexed bus configuration.
6. Peripheral I/O mode.
7. MCU reset mode.
PG0-PG7
21-28
I/O
CMOS
or
Open
Drain
These pins make up Port G. These port pins are configurable and can have the
following functions:
1. MCU I/O – standard output or input port.
2. Latched address outputs.
3. Data bus port (D8-D15) in a non-multiplexed bus configuration.
4. MCU reset mode.
VCC
9, 29,
69
Supply Voltage
GND
8, 30,
49,
50, 70
Ground pins
13/89

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]