CXD2310AR Просмотр технического описания (PDF) - Sony Semiconductor
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CXD2310AR Datasheet PDF : 16 Pages
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CXD2310AR
1. Calibration Function
In order to achieve superior linearity, the CXD2310AR has a built-in calibration circuit. In order to eliminate the
necessity for the externally input calibration pulse required by the earlier CXD2310R, a startup calibration
function and an auto calibration pulse generation function have been newly added to the CXD2310AR. Fig. 1
shows a block diagram of the calibration pulse generation circuit.
CLK
1
16
14 bit
Counter
CLR
AVDD
DQ
CO
CLR
OUT
AVDD
AVSS
VRT
VRB
RESET
CE
Sence
Amp 1
Sence
Amp 2
24 bit
Counter
CO
CLR
SEL
CAL
Fig. 1. Calibration Pulse Generation Circuit
(1) Startup Calibration Function
Over 600 calibration pulses are needed to complete the initial calibration process when the power is first
supplied to the IC. The startup calibration function automatically generates these pulses internally and
completes the initial calibration process.
The following five conditions must be satisfied to initiate the
startup calibration function.
When RESET = High and CE = Low
[V]
AVDD
5
VRT
a) The voltage between AVDD and AVSS is approximately
2.5V or more.
b) The voltage between VRT and VRB is approximately 1V
2.5
1V
0
Sence Amp 1
VRB
[t]
or more.
c) The RESET pin (Pin 15) must is high.
d) The CE pin (Pin 24) must is low.
e) Condition b is met after condition a.
Sence Amp 2
Once all five of these conditions have been met, the calibration
CLR
pulses are generated. The pulses are generated by counting 16
main clock cycles on a 14-bit counter and closing the gate when
the carry-out occurs. Therefore, the time required for startup
calibration after the above five conditions have been met is
determined by the following formula:
Startup calibration time = main clock cycle × 16 × 16,384
For example, if the main clock frequency is 14.3MHz, the time required for startup calibration is 18ms.
– 11 –
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