MBM29LV800BA-120PFTR Просмотр технического описания (PDF) - Fujitsu

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производитель

MBM29LV800BA-120PFTR

CMOS 8M (1M × 8/512K × 16) BIT

Fujitsu 

MBM29LV800TA-70/-90/-12/MBM29LV800BA-70/-90/-12

RESET

Hardware Reset

The MBM29LV800TA/BA devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse

requirement and has to be kept low (VIL) for at least 500 ns in order to properly reset the internal state machine.

Any operation in the process of being executed will be terminated and the internal state machine will be reset

to the read mode 20 µs after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the

devices require an additional tRH before it will allow read access. When the RESET pin is low, the devices will

be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware

reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please

note that the RY/BY output signal should be ignored during the RESET pulse. See Figure 12 for the timing

diagram. Refer to Temporary Sector Unprotection for additional functionality.

If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s)

cannot be used.

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