CYUSB3302 Просмотр технического описания (PDF) - Cypress Semiconductor
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CYUSB3302 Datasheet PDF : 33 Pages
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CYUSB330x
CYUSB331x
CYUSB332x
Table 3. 88-Pin QFN Pinout (continued)
Pin Name
CYUSB3314
Type
CYUSB3312 CYUSB3326
Pin#
CYUSB3328
DS3_GREEN[5]
DS3_VBUSEN_SL[5]
I/O
64
VID_SEL[1][6]
DS3_LED_SS[5]
PIN_STRAP[6]
I/O
63
NC
DS4_RXP
I
20
NC
DS4_RXM
I
19
NC
DS4_TXP O
16
NC
DS4_TXM O
17
NC
DS4_DP I/O
81
NC
DS4_DM I/O
82
DS4_OVRCURR
I
36
DS4_PWREN/PWR_EN4 I/O
35
DS4_CDP_EN[6]
DS4_AMBER[5]
I2C_DEV_ID[6]
DS4_GREEN[5]
I/O
30
DS4_VBUSEN_SL
I/O
43
VID_SEL[0][6]
DS4_LED_SS
I/O
26
RESERVED1
I
27
MODE_SEL[0]
MODE_SEL[1]
XTL_OUT
XTL_IN
RESETN
I2C_CLK
I2C_DATA
I
28
I
29
A
68
A
69
I
37
I/O
40
I/O
41
Description
CYUSB3312/3314: LED_GREEN output for DS3 port
CYUSB3326/3328: VBUS power enable output for SS port 3
This pin is called VID_SEL[1] in the pin-strap configuration mode. For pin-strap
configuration details, refer to Table 5.
LED_SS output for DS3 port
This pin is called PIN_STRAP in pin-strap configuration mode. When connected
to VDD_IO through a 10-k resistor, this pin enables pin-strap configuration mode
for HX3.
DS4 Port
SuperSpeed receive plus
SuperSpeed receive minus
SuperSpeed transmit plus
SuperSpeed transmit minus
USB 2.0 data plus
USB 2.0 data minus
CYUSB3314/3326/3328: Overcurrent detect input for DS4 port.
CYUSB3312: This pin must be pulled HIGH using a 10 k to VDD_IO.
VBUS power enable output for DS4 port. This pin is also used as power enable
output when configured in ganged power mode using the Blaster Plus tool. When
the port is disabled, this pin is in tristate.
This pin is called DS4_CDP_EN in the pin-strap configuration mode.
LED_AMBER output for DS4 port
This pin is called I2C_DEV_ID in the pin-strap configuration mode.
CYUSB3312/3314: LED_GREEN output for DS4 port
CYUSB3326/3328: VBUS power enable output for SS port 4
This pin is called VID_SEL[0] in the pin-strap configuration mode.
LED_SS output for DS4 port. The LED must be connected to GND as shown in
Figure 12 on page 18. If LED is not used, this pin must be pulled HIGH using a
10 k to VDD_IO.
This pin must be pulled HIGH using a 10 k to VDD_IO.
Mode Select, Clock, and Reset
Device operation mode select bit 0; refer to Table 4
Device operation mode select bit 1; refer to Table 4
Crystal out
Crystal in
Active LOW reset input
I2C clock
I2C data
Notes
5. This pin can be configured as a GPIO using custom firmware. For information contact www.cypress.com/support.
6. For pin-strap configuration details, refer to Table 5.
Document Number: 001-73643 Rev. *G
Page 15 of 33
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