T35L6432B Просмотр технического описания (PDF) - Taiwan Memory Technology

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производитель

T35L6432B

64K x 32 SRAM

Taiwan Memory Technology 

tm TE

CH

WRITE TIMING

CLK

AD SP

AD SC

t

KC

t

A D SS

t

KH

t

tK L

A D SH

tA D S S

t

A D SH

tA S tA H

AD DRESS

BW E

B W 1 -B W 4

A1

A2

B Y T E W R IT E sig n als are

ig n o red fo r first cy cle w h en

A D S P in itialtes b u rst

GW

CE

(N o te2 )

t

CES

t

CEH

ADV

(N o te4 )

T35L6432B

A D S C ex ten d s b u rst

tA D S S

t

A D SH

tW S tW H

(N o te5 )

A3

tt

WS WH

A D V suspn ds burst

tA A S tA A H

OE

(N o te3 )

tD S

t

DH

D

H ig h -Z

D (A 1)

tO E H S

D (A 2)

D (A 2+ 1)

(N o te1 )

D (A 2+ 1)

D (A 2+ 2)

D (A 2+ 3)

D (A 3)

D (A 3+ 1)

D (A 3+ 2)

Q

BURST READ

S in g le W R IT E

B U R S T W R IT E

E x ten d B U R S T W R IT E

:D o n 't c a re

:U N D E F IN E D

Note: 1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst

address following A2.

2. CE2 and CE2 have timing identical to CE . On this diagram, when CE is LOW , CE2 is

LOW and CE2 is HIGH. When CE is HIGH , CE2 is HIGH and CE2 is LOW.

3. OE must be HIGH before the input data setup and hold HIGH throughout the data hold time.

This prevents input/output data contention for the time period to the byte write enable inputs being

sampled.

4. ADV must be HIGH to permit a WRITE to the loaded address.

5. Full width WRITE can be initiated by GW LOW or GW HIGH and BWE , BW1- BW4

LOW.

Taiwan Memory Technology, Inc. reserves the right P. 13

to change products or specifications without notice.

Publication Date: JUL. 2002

Revision: A

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