W77C32-25 Просмотр технического описания (PDF) - Winbond
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W77C32-25 Datasheet PDF : 71 Pages
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Preliminary W77C32
MOVX Characteristics Using Strech Memory Cycles
PARAMETER
SYM.
VARIABLE
CLOCK
MIN.
VARIABLE UNITS STRECH
CLOCK
MAX.
Data Access ALE Pulse Width
Address Hold After ALE Low for
MOVX Write
tLLHL2
tLLAX2
1.5 tCLCL - 5
2.0 tCLCL - 5
0.5 tCLCL - 5
nS
tMCS = 0
tMCS > 0
nS
RD Pulse Width
WR Pulse Width
RD Low to Valid Data In
Data Hold after Read
Data Float after Read
ALE Low to Valid Data In
tRLRH
2.0 tCLCL - 5
nS
tMCS - 10
tWLWH
2.0 tCLCL - 5
nS
tMCS - 10
tRLDV
2.0 tCLCL - 20
nS
tMCS - 20
tRHDX
0
nS
tRHDZ
tCLCL - 5
nS
2.0 tCLCL - 5
tLLDV
2.5 tCLCL - 5
nS
tMCS + 2tCLCL
- 40
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
Port 0 Address to Valid Data In
Port 2 Address to Valid Data In
ALE Low to RD or WR Low
Port 0 Address to RD or WR Low
Port 2 Address to RD or WR Low
Data Valid to WR Transition
Data Hold after Write
RD Low to Address Float
tAVDV1
3.0 tCLCL - 20
nS
2.0tCLCL - 5
tAVDV2
3.5 tCLCL - 20
nS
2.5 tCLCL - 5
tLLWL
0.5 tCLCL - 5
0.5 tCLCL + 5
nS
1.5 tCLCL - 5 1.5 tCLCL + 5
tAVWL
tCLCL - 5
nS
2.0 tCLCL - 5
tAVWL2
1.5 tCLCL - 5
nS
2.5 tCLCL - 5
tQVWX
-5
nS
1.0 tCLCL - 5
tWHQX
tCLCL - 5
nS
2.0 tCLCL - 5
tRLAZ
0.5 tCLCL - 5
nS
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
tMCS = 0
tMCS > 0
RD or WR High to ALE High
tWHLH
0
10
nS
1.0 tCLCL - 5 1.0 tCLCL + 5
tMCS = 0
tMCS > 0
Note: tMCS is a time period related to the Stretch memory cycle selection. The following table shows the time period of tMCS for each
selection of the Stretch value.
- 65 -
Publication Release Date: March 1999
Revision A1
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