W77C32-25 Просмотр технического описания (PDF) - Winbond
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W77C32-25 Datasheet PDF : 71 Pages
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Preliminary W77C32
RI: Receive interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or
halfway through the stop bits time in the other modes during serial reception. However the
restrictions of SM2 apply to this bit. This bit can be cleared only by software
Serial Data Buffer
Bit:
7
6
SBUF. SBUF.
7
6
Mnemonic: SBUF
5
SBUF.
5
4
SBUF.
4
3
SBUF.
3
2
SBUF.
2
1
0
SBUF. SBUF.
1
0
Address: 99h
SBUF.7-0: Serial data on the serial port 0 is read from or written to this location. It actually consists of
two separate internal 8-bit registers. One is the receive resister, and the other is the
transmit buffer. Any read access gets data from the receive data buffer, while write access
is to the transmit data buffer.
Port 2
Bit:
7
6
5
4
3
2
1
0
P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0
Mnemonic: P2
Address: A0h
P2.7-0: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides the upper
address bits for accesses to external memory.
Port 4
Bit:
7
6
5
4
-
-
-
-
Mnemonic: P4
P4.3-0: Port 4 is a bi-directional I/O port with internal pull-ups.
3
P4.3
2
1
0
P4.2 P4.1 P4.0
Address: A5h
Interrupt Enable
Bit:
7
6
5
4
3
EA ES1 ET2 ES ET1
EA:
ES1:
ET2:
ES:
ET1:
EX1:
ET0:
EX0:
Mnemonic: IE
Global enable. Enable/disable all interrupts except for PFI.
Enable Serial Port 1 interrupt.
Enable Timer 2 interrupt.
Enable Serial Port 0 interrupt.
Enable Timer 1 interrupt
Enable external interrupt 1
Enable Timer 0 interrupt
Enable external interrupt 0
2
1
0
EX1 ET0 EX0
Address: A8h
- 15 -
Publication Release Date: March 1999
Revision A1
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