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DS2436 Просмотр технического описания (PDF) - Maxim Integrated

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производитель
DS2436
MaximIC
Maxim Integrated MaximIC
DS2436 Datasheet PDF : 29 Pages
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DS2436
CRC GENERATION
The DS2436 has an 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master can
compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within
the DS2436 to determine if the ROM data has been received error-free by the bus master. Additionally,
each page read appends one CRC byte. The equivalent polynomial function of this CRC is:
CRC = X8 + X5 + X4 + 1
Xn = bit at the n-th stage
+ = "exclusive-or" function
The DS2436 also generates an 8-bit CRC value using the same polynomial function shown above and
provides this value to the bus master to validate the transfer of data bytes. In each case where a CRC is
used for data transfer validation, the bus master must calculate a CRC value using the polynomial
function given above and compare the calculated value to either the 8-bit CRC value stored in the 64-bit
ROM portion of the DS2436 (for ROM reads) or the 8-bit CRC value computed within the DS2436
scratchpad (which is read as a 33rd byte when the scratchpad is read). The comparison of CRC values and
decision to continue with an operation are determined entirely by the bus master. There is no circuitry
inside the DS2436 that prevents a command sequence from proceeding if the CRC stored in or calculated
by the DS2436 does not match the value generated by the bus master. Proper use of the CRC can result in
a communication channel with a very high level of integrity.
The 1-Wire CRC can be generated using a polynomial generator consisting of a shift register and XOR
gates as shown in Figure 6. Additional information about the Dallas 1-Wire CRC is available in an
application note entitled “Understanding and Using Cyclic Redundancy Checks with Dallas
Semiconductor Touch Memory Products” (App Note #27).
In the circuit in Figure 6, the shift register bits are initialized to 0. Then, starting with the least significant
bit of the family code, 1 bit at a time is shifted in. After the 8th bit of the family code has been entered,
the serial number is entered. After the 48th bit of the serial number has been entered, the shift register
contains the CRC value. Shifting in the 8 bits of CRC should return the shift register to all 0s.
64-BIT LASERED ROM Figure 4
8-BIT CRC CODE
48-BIT SERIAL NUMBER
8-BIT FAMILY CODE (1B)
MSB
LSB MSB
LSB MSB
LSB
14 of 29

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