DS21554 Просмотр технического описания (PDF) - Maxim Integrated
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DS21554 Datasheet PDF : 124 Pages
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
3.1.3.
Parallel Control Port Pins
Signal Name:
INT
Signal Description: Interrupt
Signal Type:
Output
Active-low, open-drain output that flags host controller during conditions and change of conditions
defined in the Status Registers 1 and 2 and the HDLC Status Register.
Signal Name:
FMS
Signal Description: Framer Mode Select
Signal Type:
Input
Selects the DS2154 mode when high or the DS21354/DS21554 mode when low. If high, the JTRST is
internally pulled low. If low, JTRST has normal JTAG functionality. This pin has a 10kW pullup resistor.
Signal Name:
TEST
Signal Description: Tri-State Control
Signal Type:
Input
Set high to tri-state all output and I/O pins (including the parallel control port). Set low for normal
operation. Useful in board-level testing.
Signal Name:
MUX
Signal Description: Bus Operation
Signal Type:
Input
Set low to select nonmultiplexed bus operation. Set high to select multiplexed bus operation.
Signal Name:
AD0 to AD7
Signal Description: Data Bus [D0 to D7] or Address/Data Bus
Signal Type:
Input
In nonmultiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation
(MUX = 1), serves as an 8-bit multiplexed address/data bus.
Signal Name:
A0 to A6
Signal Description: Address Bus
Signal Type:
Input
In nonmultiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation
(MUX = 1), these pins are not used and should be tied low.
Signal Name:
BTS
Signal Description: Bus Type Select
Signal Type:
Input
Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the
function of the RD (DS), ALE (AS), and WR (R/W) pins. If BTS = 1, then these pins assume the function
listed in parentheses ().
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